radv: init states from pTessellationState at only one place
It's part of the pre-rasterization state of graphics pipeline libs. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16552>
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@ -113,18 +113,6 @@ radv_pipeline_get_multisample_state(const struct radv_pipeline *pipeline,
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return NULL;
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}
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static const VkPipelineTessellationStateCreateInfo *
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radv_pipeline_get_tessellation_state(const struct radv_pipeline *pipeline,
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const VkGraphicsPipelineCreateInfo *pCreateInfo)
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{
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const VkShaderStageFlagBits tess_stages = VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT |
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VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT;
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if ((pipeline->active_stages & tess_stages) == tess_stages)
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return pCreateInfo->pTessellationState;
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return NULL;
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}
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static bool
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radv_pipeline_has_ds_attachments(const VkGraphicsPipelineCreateInfo *pCreateInfo)
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{
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@ -1695,6 +1683,29 @@ radv_pipeline_init_vertex_input_interface(struct radv_pipeline *pipeline,
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return vi_info;
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}
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static struct radv_pre_raster_info
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radv_pipeline_init_pre_raster_info(struct radv_pipeline *pipeline,
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const VkGraphicsPipelineCreateInfo *pCreateInfo)
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{
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const VkPipelineTessellationStateCreateInfo *ts = pCreateInfo->pTessellationState;
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const VkShaderStageFlagBits tess_stages = VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT |
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VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT;
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struct radv_pre_raster_info pre_rast_info = {0};
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/* Tessellation */
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if ((pipeline->active_stages & tess_stages) == tess_stages) {
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pre_rast_info.tess.patch_control_points = ts->patchControlPoints;
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const VkPipelineTessellationDomainOriginStateCreateInfo *domain_origin_state =
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vk_find_struct_const(ts->pNext, PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
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if (domain_origin_state) {
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pre_rast_info.tess.domain_origin = domain_origin_state->domainOrigin;
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}
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}
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return pre_rast_info;
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}
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static void
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radv_pipeline_init_input_assembly_state(struct radv_pipeline *pipeline,
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const VkGraphicsPipelineCreateInfo *pCreateInfo,
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@ -3106,6 +3117,7 @@ static struct radv_pipeline_key
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radv_generate_graphics_pipeline_key(const struct radv_pipeline *pipeline,
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const VkGraphicsPipelineCreateInfo *pCreateInfo,
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const struct radv_vertex_input_info *vi_info,
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const struct radv_pre_raster_info *pre_rast_info,
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const struct radv_blend_state *blend)
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{
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struct radv_device *device = pipeline->device;
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@ -3137,10 +3149,7 @@ radv_generate_graphics_pipeline_key(const struct radv_pipeline *pipeline,
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key.vs.vertex_binding_align[i] = vi_info->vertex_binding_align[i];
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}
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const VkPipelineTessellationStateCreateInfo *tess =
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radv_pipeline_get_tessellation_state(pipeline, pCreateInfo);
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if (tess)
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key.tcs.tess_input_vertices = tess->patchControlPoints;
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key.tcs.tess_input_vertices = pre_rast_info->tess.patch_control_points;
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const VkPipelineMultisampleStateCreateInfo *vkms =
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radv_pipeline_get_multisample_state(pipeline, pCreateInfo);
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@ -5803,14 +5812,15 @@ radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs, struct radeon_
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static void
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radv_pipeline_generate_tess_state(struct radeon_cmdbuf *ctx_cs,
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const struct radv_pipeline *pipeline,
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const VkGraphicsPipelineCreateInfo *pCreateInfo)
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const VkGraphicsPipelineCreateInfo *pCreateInfo,
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const struct radv_pre_raster_info *pre_rast_info)
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{
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struct radv_shader *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
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unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
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unsigned num_tcs_input_cp, num_tcs_output_cp, num_patches;
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unsigned ls_hs_config;
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num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
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num_tcs_input_cp = pre_rast_info->tess.patch_control_points;
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num_tcs_output_cp =
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pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; // TCS VERTICES OUT
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num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.num_tess_patches;
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@ -5853,12 +5863,7 @@ radv_pipeline_generate_tess_state(struct radeon_cmdbuf *ctx_cs,
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}
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bool ccw = tes->info.tes.ccw;
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const VkPipelineTessellationDomainOriginStateCreateInfo *domain_origin_state =
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vk_find_struct_const(pCreateInfo->pTessellationState,
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PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
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if (domain_origin_state &&
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domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT)
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if (pre_rast_info->tess.domain_origin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT)
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ccw = !ccw;
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if (tes->info.tes.point_mode)
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@ -6473,7 +6478,8 @@ radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
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const VkGraphicsPipelineCreateInfo *pCreateInfo,
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const struct radv_blend_state *blend,
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const struct radv_depth_stencil_state *ds_state,
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uint32_t vgt_gs_out_prim_type)
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uint32_t vgt_gs_out_prim_type,
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const struct radv_pre_raster_info *pre_rast_info)
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{
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struct radeon_cmdbuf *ctx_cs = &pipeline->ctx_cs;
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struct radeon_cmdbuf *cs = &pipeline->cs;
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@ -6493,7 +6499,7 @@ radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
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if (radv_pipeline_has_tess(pipeline)) {
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radv_pipeline_generate_tess_shaders(ctx_cs, cs, pipeline);
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radv_pipeline_generate_tess_state(ctx_cs, pipeline, pCreateInfo);
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radv_pipeline_generate_tess_state(ctx_cs, pipeline, pCreateInfo, pre_rast_info);
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}
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radv_pipeline_generate_geometry_shader(ctx_cs, cs, pipeline);
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@ -6731,11 +6737,14 @@ radv_graphics_pipeline_init(struct radv_pipeline *pipeline, struct radv_device *
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struct radv_vertex_input_info vi_info =
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radv_pipeline_init_vertex_input_interface(pipeline, pCreateInfo);
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struct radv_pre_raster_info pre_rast_info =
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radv_pipeline_init_pre_raster_info(pipeline, pCreateInfo);
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const VkPipelineCreationFeedbackCreateInfo *creation_feedback =
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vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO);
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struct radv_pipeline_key key =
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radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &vi_info, &blend);
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radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &vi_info, &pre_rast_info, &blend);
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result = radv_create_shaders(pipeline, pipeline_layout, device, cache, &key, pCreateInfo->pStages,
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pCreateInfo->stageCount, pCreateInfo->flags, NULL,
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@ -6789,8 +6798,7 @@ radv_graphics_pipeline_init(struct radv_pipeline *pipeline, struct radv_device *
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}
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if (radv_pipeline_has_tess(pipeline)) {
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pipeline->graphics.tess_patch_control_points =
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pCreateInfo->pTessellationState->patchControlPoints;
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pipeline->graphics.tess_patch_control_points = pre_rast_info.tess.patch_control_points;
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}
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if (!radv_pipeline_has_mesh(pipeline))
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@ -6819,7 +6827,8 @@ radv_graphics_pipeline_init(struct radv_pipeline *pipeline, struct radv_device *
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radv_pipeline_init_extra(pipeline, pCreateInfo, extra, &blend, &ds_state, &vgt_gs_out_prim_type);
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}
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radv_pipeline_generate_pm4(pipeline, pCreateInfo, &blend, &ds_state, vgt_gs_out_prim_type);
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radv_pipeline_generate_pm4(pipeline, pCreateInfo, &blend, &ds_state, vgt_gs_out_prim_type,
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&pre_rast_info);
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return result;
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}
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@ -1877,6 +1877,13 @@ struct radv_vertex_input_info {
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bool primitive_restart_enable;
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};
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struct radv_pre_raster_info {
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struct {
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uint32_t patch_control_points;
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VkTessellationDomainOrigin domain_origin;
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} tess;
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};
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struct radv_pipeline {
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struct vk_object_base base;
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enum radv_pipeline_type type;
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