i965: Print disassembly after compaction.
Reviewed-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
parent
b5fd762474
commit
f0f7fb181f
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@ -46,6 +46,7 @@ extern "C" {
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#include "brw_eu.h"
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#include "brw_eu.h"
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#include "brw_wm.h"
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#include "brw_wm.h"
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#include "brw_shader.h"
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#include "brw_shader.h"
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#include "intel_asm_printer.h"
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}
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}
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#include "gen8_generator.h"
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#include "gen8_generator.h"
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#include "glsl/glsl_types.h"
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#include "glsl/glsl_types.h"
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@ -209,13 +210,6 @@ public:
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fs_reg dst;
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fs_reg dst;
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fs_reg src[3];
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fs_reg src[3];
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/** @{
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* Annotation for the generated IR. One of the two can be set.
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*/
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const void *ir;
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const char *annotation;
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/** @} */
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uint32_t texture_offset; /**< Texture offset bitfield */
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uint32_t texture_offset; /**< Texture offset bitfield */
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uint32_t offset; /* spill/unspill offset */
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uint32_t offset; /* spill/unspill offset */
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@ -611,7 +605,8 @@ public:
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unsigned *assembly_size);
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unsigned *assembly_size);
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private:
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private:
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void generate_code(exec_list *instructions);
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void generate_code(exec_list *instructions,
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struct annotation_info *annotation);
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void generate_fb_write(fs_inst *inst);
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void generate_fb_write(fs_inst *inst);
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void generate_blorp_fb_write(fs_inst *inst);
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void generate_blorp_fb_write(fs_inst *inst);
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void generate_pixel_xy(struct brw_reg dst, bool is_x);
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void generate_pixel_xy(struct brw_reg dst, bool is_x);
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@ -738,7 +733,8 @@ public:
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unsigned *assembly_size);
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unsigned *assembly_size);
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private:
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private:
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void generate_code(exec_list *instructions);
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void generate_code(exec_list *instructions,
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struct annotation_info *annotation);
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void generate_fb_write(fs_inst *inst);
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void generate_fb_write(fs_inst *inst);
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void generate_linterp(fs_inst *inst, struct brw_reg dst,
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void generate_linterp(fs_inst *inst, struct brw_reg dst,
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struct brw_reg *src);
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struct brw_reg *src);
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@ -1322,12 +1322,9 @@ fs_generator::generate_untyped_surface_read(fs_inst *inst, struct brw_reg dst,
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}
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}
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void
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void
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fs_generator::generate_code(exec_list *instructions)
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fs_generator::generate_code(exec_list *instructions,
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struct annotation_info *annotation)
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{
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{
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int last_native_insn_offset = p->next_insn_offset;
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const char *last_annotation_string = NULL;
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const void *last_annotation_ir = NULL;
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if (unlikely(debug_flag)) {
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if (unlikely(debug_flag)) {
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if (prog) {
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if (prog) {
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fprintf(stderr,
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fprintf(stderr,
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@ -1352,47 +1349,8 @@ fs_generator::generate_code(exec_list *instructions)
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fs_inst *inst = (fs_inst *)node;
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fs_inst *inst = (fs_inst *)node;
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struct brw_reg src[3], dst;
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struct brw_reg src[3], dst;
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if (unlikely(debug_flag)) {
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if (unlikely(debug_flag))
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foreach_list(node, &cfg->block_list) {
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annotate(brw, annotation, cfg, inst, p->next_insn_offset);
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bblock_link *link = (bblock_link *)node;
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bblock_t *block = link->block;
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if (block->start == inst) {
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fprintf(stderr, " START B%d", block->block_num);
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foreach_list(predecessor_node, &block->parents) {
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bblock_link *predecessor_link =
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(bblock_link *)predecessor_node;
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bblock_t *predecessor_block = predecessor_link->block;
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fprintf(stderr, " <-B%d", predecessor_block->block_num);
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}
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fprintf(stderr, "\n");
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}
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}
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if (last_annotation_ir != inst->ir) {
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last_annotation_ir = inst->ir;
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if (last_annotation_ir) {
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fprintf(stderr, " ");
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if (prog)
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((ir_instruction *)inst->ir)->fprint(stderr);
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else {
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const prog_instruction *fpi;
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fpi = (const prog_instruction *)inst->ir;
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fprintf(stderr, "%d: ",
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(int)(fpi - (fp ? fp->Base.Instructions : 0)));
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_mesa_fprint_instruction_opt(stderr,
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fpi,
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0, PROG_PRINT_DEBUG, NULL);
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}
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fprintf(stderr, "\n");
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}
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}
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if (last_annotation_string != inst->annotation) {
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last_annotation_string = inst->annotation;
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if (last_annotation_string)
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fprintf(stderr, " %s\n", last_annotation_string);
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}
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}
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for (unsigned int i = 0; i < 3; i++) {
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for (unsigned int i = 0; i < 3; i++) {
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src[i] = brw_reg_from_fs_reg(&inst->src[i]);
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src[i] = brw_reg_from_fs_reg(&inst->src[i]);
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@ -1792,7 +1750,9 @@ fs_generator::generate_code(exec_list *instructions)
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/* This is the place where the final HALT needs to be inserted if
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/* This is the place where the final HALT needs to be inserted if
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* we've emitted any discards. If not, this will emit no code.
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* we've emitted any discards. If not, this will emit no code.
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*/
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*/
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patch_discard_jumps_to_fb_writes();
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if (!patch_discard_jumps_to_fb_writes()) {
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annotation->ann_count--;
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}
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break;
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break;
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default:
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default:
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@ -1804,44 +1764,10 @@ fs_generator::generate_code(exec_list *instructions)
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}
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}
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abort();
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abort();
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}
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}
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if (unlikely(debug_flag)) {
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brw_disassemble(brw, p->store, last_native_insn_offset, p->next_insn_offset, stderr);
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foreach_list(node, &cfg->block_list) {
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bblock_link *link = (bblock_link *)node;
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bblock_t *block = link->block;
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if (block->end == inst) {
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fprintf(stderr, " END B%d", block->block_num);
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foreach_list(successor_node, &block->children) {
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bblock_link *successor_link =
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(bblock_link *)successor_node;
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bblock_t *successor_block = successor_link->block;
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fprintf(stderr, " ->B%d", successor_block->block_num);
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}
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fprintf(stderr, "\n");
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}
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}
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}
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last_native_insn_offset = p->next_insn_offset;
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}
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if (unlikely(debug_flag)) {
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fprintf(stderr, "\n");
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}
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}
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brw_set_uip_jip(p);
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brw_set_uip_jip(p);
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annotation_finalize(annotation, p->next_insn_offset);
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/* OK, while the INTEL_DEBUG=wm above is very nice for debugging FS
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* emit issues, it doesn't get the jump distances into the output,
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* which is often something we want to debug. So this is here in
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* case you're doing that.
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*/
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if (0) {
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brw_disassemble(brw, p->store, 0, p->next_insn_offset, stderr);
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}
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}
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}
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const unsigned *
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const unsigned *
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@ -1851,10 +1777,21 @@ fs_generator::generate_assembly(exec_list *simd8_instructions,
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{
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{
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assert(simd8_instructions || simd16_instructions);
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assert(simd8_instructions || simd16_instructions);
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const struct gl_program *prog = fp ? &fp->Base : NULL;
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if (simd8_instructions) {
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if (simd8_instructions) {
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struct annotation_info annotation;
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memset(&annotation, 0, sizeof(annotation));
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dispatch_width = 8;
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dispatch_width = 8;
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generate_code(simd8_instructions);
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generate_code(simd8_instructions, &annotation);
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brw_compact_instructions(p, 0, 0, NULL);
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brw_compact_instructions(p, 0, annotation.ann_count, annotation.ann);
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if (unlikely(debug_flag)) {
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dump_assembly(p->store, annotation.ann_count, annotation.ann,
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brw, prog, brw_disassemble);
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ralloc_free(annotation.ann);
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}
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}
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}
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if (simd16_instructions) {
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if (simd16_instructions) {
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@ -1868,9 +1805,19 @@ fs_generator::generate_assembly(exec_list *simd8_instructions,
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brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
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brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
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struct annotation_info annotation;
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memset(&annotation, 0, sizeof(annotation));
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dispatch_width = 16;
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dispatch_width = 16;
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generate_code(simd16_instructions);
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generate_code(simd16_instructions, &annotation);
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brw_compact_instructions(p, prog_data->prog_offset_16, 0, NULL);
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brw_compact_instructions(p, prog_data->prog_offset_16,
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annotation.ann_count, annotation.ann);
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if (unlikely(debug_flag)) {
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dump_assembly(p->store, annotation.ann_count, annotation.ann,
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brw, prog, brw_disassemble);
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ralloc_free(annotation.ann);
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}
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}
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}
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return brw_get_program(p, assembly_size);
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return brw_get_program(p, assembly_size);
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@ -28,6 +28,7 @@ extern "C" {
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#include "brw_vs.h"
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#include "brw_vs.h"
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#include "brw_vec4_gs.h"
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#include "brw_vec4_gs.h"
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#include "brw_fs.h"
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#include "brw_fs.h"
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#include "brw_cfg.h"
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#include "glsl/ir_optimization.h"
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#include "glsl/ir_optimization.h"
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#include "glsl/glsl_parser_extras.h"
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#include "glsl/glsl_parser_extras.h"
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#include "main/shaderapi.h"
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#include "main/shaderapi.h"
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@ -760,3 +761,56 @@ backend_visitor::assign_common_binding_table_offsets(uint32_t next_binding_table
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/* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
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/* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
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}
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}
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void annotate(struct brw_context *brw,
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struct annotation_info *annotation, cfg_t *cfg,
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backend_instruction *inst, unsigned offset)
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{
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if (annotation->ann_size <= annotation->ann_count) {
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annotation->ann_size = MAX2(1024, annotation->ann_size * 2);
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annotation->ann = reralloc(annotation->mem_ctx, annotation->ann,
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struct annotation, annotation->ann_size);
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if (!annotation->ann)
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return;
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}
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struct annotation *ann = &annotation->ann[annotation->ann_count++];
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ann->offset = offset;
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ann->ir = inst->ir;
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ann->annotation = inst->annotation;
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if (cfg->blocks[annotation->cur_block]->start == inst) {
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ann->block_start = cfg->blocks[annotation->cur_block];
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}
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/* There is no hardware DO instruction on Gen6+, so since DO always
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* starts a basic block, we need to set the .block_start of the next
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* instruction's annotation with a pointer to the bblock started by
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* the DO.
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*
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* There's also only complication from emitting an annotation without
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* a corresponding hardware instruction to disassemble.
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*/
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if (brw->gen >= 6 && inst->opcode == BRW_OPCODE_DO) {
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annotation->ann_count--;
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}
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if (cfg->blocks[annotation->cur_block]->end == inst) {
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ann->block_end = cfg->blocks[annotation->cur_block];
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annotation->cur_block++;
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}
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}
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void
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annotation_finalize(struct annotation_info *annotation,
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unsigned next_inst_offset)
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{
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if (!annotation->ann_count)
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return;
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if (annotation->ann_count == annotation->ann_size) {
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annotation->ann = reralloc(annotation->mem_ctx, annotation->ann,
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struct annotation, annotation->ann_size + 1);
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}
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annotation->ann[annotation->ann_count].offset = next_inst_offset;
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}
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@ -25,6 +25,7 @@
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#include "brw_defines.h"
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#include "brw_defines.h"
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#include "main/compiler.h"
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#include "main/compiler.h"
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#include "glsl/ir.h"
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#include "glsl/ir.h"
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#include "intel_asm_printer.h"
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#pragma once
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#pragma once
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@ -40,6 +41,8 @@ enum PACKED register_file {
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#ifdef __cplusplus
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#ifdef __cplusplus
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class cfg_t;
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class backend_instruction : public exec_node {
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class backend_instruction : public exec_node {
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public:
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public:
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bool is_tex() const;
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bool is_tex() const;
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uint8_t predicate;
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uint8_t predicate;
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bool predicate_inverse;
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bool predicate_inverse;
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bool writes_accumulator; /**< instruction implicitly writes accumulator */
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bool writes_accumulator; /**< instruction implicitly writes accumulator */
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/** @{
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* Annotation for the generated IR. One of the two can be set.
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*/
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const void *ir;
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const char *annotation;
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/** @} */
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};
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};
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enum instruction_scheduler_mode {
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enum instruction_scheduler_mode {
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@ -108,6 +118,11 @@ public:
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uint32_t brw_texture_offset(struct gl_context *ctx, ir_constant *offset);
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uint32_t brw_texture_offset(struct gl_context *ctx, ir_constant *offset);
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void annotate(struct brw_context *brw,
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struct annotation_info *annotation, cfg_t *cfg,
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backend_instruction *inst, unsigned offset);
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void annotation_finalize(struct annotation_info *annotation, unsigned offset);
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#endif /* __cplusplus */
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#endif /* __cplusplus */
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int brw_type_for_base_type(const struct glsl_type *type);
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int brw_type_for_base_type(const struct glsl_type *type);
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@ -36,6 +36,7 @@ extern "C" {
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#include "brw_context.h"
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#include "brw_context.h"
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#include "brw_eu.h"
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#include "brw_eu.h"
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#include "intel_asm_printer.h"
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#ifdef __cplusplus
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#ifdef __cplusplus
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}; /* extern "C" */
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}; /* extern "C" */
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@ -260,12 +261,6 @@ public:
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int base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
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int base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
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uint32_t offset; /* spill/unspill offset */
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uint32_t offset; /* spill/unspill offset */
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/** @{
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* Annotation for the generated IR. One of the two can be set.
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*/
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const void *ir;
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const char *annotation;
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/** @} */
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bool is_send_from_grf();
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bool is_send_from_grf();
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bool can_reswizzle_dst(int dst_writemask, int swizzle, int swizzle_mask);
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bool can_reswizzle_dst(int dst_writemask, int swizzle, int swizzle_mask);
|
||||||
|
@ -650,7 +645,8 @@ public:
|
||||||
const unsigned *generate_assembly(exec_list *insts, unsigned *asm_size);
|
const unsigned *generate_assembly(exec_list *insts, unsigned *asm_size);
|
||||||
|
|
||||||
private:
|
private:
|
||||||
void generate_code(exec_list *instructions);
|
void generate_code(exec_list *instructions,
|
||||||
|
struct annotation_info *annotation);
|
||||||
void generate_vec4_instruction(vec4_instruction *inst,
|
void generate_vec4_instruction(vec4_instruction *inst,
|
||||||
struct brw_reg dst,
|
struct brw_reg dst,
|
||||||
struct brw_reg *src);
|
struct brw_reg *src);
|
||||||
|
@ -751,7 +747,8 @@ public:
|
||||||
const unsigned *generate_assembly(exec_list *insts, unsigned *asm_size);
|
const unsigned *generate_assembly(exec_list *insts, unsigned *asm_size);
|
||||||
|
|
||||||
private:
|
private:
|
||||||
void generate_code(exec_list *instructions);
|
void generate_code(exec_list *instructions,
|
||||||
|
struct annotation_info *annotation);
|
||||||
void generate_vec4_instruction(vec4_instruction *inst,
|
void generate_vec4_instruction(vec4_instruction *inst,
|
||||||
struct brw_reg dst,
|
struct brw_reg dst,
|
||||||
struct brw_reg *src);
|
struct brw_reg *src);
|
||||||
|
|
|
@ -21,6 +21,7 @@
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include "brw_vec4.h"
|
#include "brw_vec4.h"
|
||||||
|
#include "brw_cfg.h"
|
||||||
|
|
||||||
extern "C" {
|
extern "C" {
|
||||||
#include "brw_eu.h"
|
#include "brw_eu.h"
|
||||||
|
@ -1260,12 +1261,9 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
vec4_generator::generate_code(exec_list *instructions)
|
vec4_generator::generate_code(exec_list *instructions,
|
||||||
|
struct annotation_info *annotation)
|
||||||
{
|
{
|
||||||
int last_native_insn_offset = 0;
|
|
||||||
const char *last_annotation_string = NULL;
|
|
||||||
const void *last_annotation_ir = NULL;
|
|
||||||
|
|
||||||
if (unlikely(debug_flag)) {
|
if (unlikely(debug_flag)) {
|
||||||
if (shader_prog) {
|
if (shader_prog) {
|
||||||
fprintf(stderr, "Native code for %s vertex shader %d:\n",
|
fprintf(stderr, "Native code for %s vertex shader %d:\n",
|
||||||
|
@ -1276,33 +1274,16 @@ vec4_generator::generate_code(exec_list *instructions)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
cfg_t *cfg = NULL;
|
||||||
|
if (unlikely(debug_flag))
|
||||||
|
cfg = new(mem_ctx) cfg_t(instructions);
|
||||||
|
|
||||||
foreach_list(node, instructions) {
|
foreach_list(node, instructions) {
|
||||||
vec4_instruction *inst = (vec4_instruction *)node;
|
vec4_instruction *inst = (vec4_instruction *)node;
|
||||||
struct brw_reg src[3], dst;
|
struct brw_reg src[3], dst;
|
||||||
|
|
||||||
if (unlikely(debug_flag)) {
|
if (unlikely(debug_flag))
|
||||||
if (last_annotation_ir != inst->ir) {
|
annotate(brw, annotation, cfg, inst, p->next_insn_offset);
|
||||||
last_annotation_ir = inst->ir;
|
|
||||||
if (last_annotation_ir) {
|
|
||||||
fprintf(stderr, " ");
|
|
||||||
if (shader_prog) {
|
|
||||||
((ir_instruction *) last_annotation_ir)->fprint(stderr);
|
|
||||||
} else {
|
|
||||||
const prog_instruction *vpi;
|
|
||||||
vpi = (const prog_instruction *) inst->ir;
|
|
||||||
fprintf(stderr, "%d: ", (int)(vpi - prog->Instructions));
|
|
||||||
_mesa_fprint_instruction_opt(stderr, vpi, 0,
|
|
||||||
PROG_PRINT_DEBUG, NULL);
|
|
||||||
}
|
|
||||||
fprintf(stderr, "\n");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (last_annotation_string != inst->annotation) {
|
|
||||||
last_annotation_string = inst->annotation;
|
|
||||||
if (last_annotation_string)
|
|
||||||
fprintf(stderr, " %s\n", last_annotation_string);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
for (unsigned int i = 0; i < 3; i++) {
|
for (unsigned int i = 0; i < 3; i++) {
|
||||||
src[i] = inst->get_src(this->prog_data, i);
|
src[i] = inst->get_src(this->prog_data, i);
|
||||||
|
@ -1332,38 +1313,29 @@ vec4_generator::generate_code(exec_list *instructions)
|
||||||
if (inst->no_dd_check)
|
if (inst->no_dd_check)
|
||||||
last->header.dependency_control |= BRW_DEPENDENCY_NOTCHECKED;
|
last->header.dependency_control |= BRW_DEPENDENCY_NOTCHECKED;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (unlikely(debug_flag)) {
|
|
||||||
brw_disassemble(brw, p->store,
|
|
||||||
last_native_insn_offset, p->next_insn_offset, stderr);
|
|
||||||
}
|
|
||||||
|
|
||||||
last_native_insn_offset = p->next_insn_offset;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (unlikely(debug_flag)) {
|
|
||||||
fprintf(stderr, "\n");
|
|
||||||
}
|
}
|
||||||
|
|
||||||
brw_set_uip_jip(p);
|
brw_set_uip_jip(p);
|
||||||
|
annotation_finalize(annotation, p->next_insn_offset);
|
||||||
/* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS
|
|
||||||
* emit issues, it doesn't get the jump distances into the output,
|
|
||||||
* which is often something we want to debug. So this is here in
|
|
||||||
* case you're doing that.
|
|
||||||
*/
|
|
||||||
if (0 && unlikely(debug_flag)) {
|
|
||||||
brw_disassemble(brw, p->store, 0, p->next_insn_offset, stderr);
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
const unsigned *
|
const unsigned *
|
||||||
vec4_generator::generate_assembly(exec_list *instructions,
|
vec4_generator::generate_assembly(exec_list *instructions,
|
||||||
unsigned *assembly_size)
|
unsigned *assembly_size)
|
||||||
{
|
{
|
||||||
|
struct annotation_info annotation;
|
||||||
|
memset(&annotation, 0, sizeof(annotation));
|
||||||
|
|
||||||
brw_set_access_mode(p, BRW_ALIGN_16);
|
brw_set_access_mode(p, BRW_ALIGN_16);
|
||||||
generate_code(instructions);
|
generate_code(instructions, &annotation);
|
||||||
brw_compact_instructions(p, 0, 0, NULL);
|
brw_compact_instructions(p, 0, annotation.ann_count, annotation.ann);
|
||||||
|
|
||||||
|
if (unlikely(debug_flag)) {
|
||||||
|
dump_assembly(p->store, annotation.ann_count, annotation.ann,
|
||||||
|
brw, prog, brw_disassemble);
|
||||||
|
ralloc_free(annotation.ann);
|
||||||
|
}
|
||||||
|
|
||||||
return brw_get_program(p, assembly_size);
|
return brw_get_program(p, assembly_size);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -884,12 +884,9 @@ gen8_fs_generator::generate_untyped_surface_read(fs_inst *ir,
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
gen8_fs_generator::generate_code(exec_list *instructions)
|
gen8_fs_generator::generate_code(exec_list *instructions,
|
||||||
|
struct annotation_info *annotation)
|
||||||
{
|
{
|
||||||
int last_native_inst_offset = next_inst_offset;
|
|
||||||
const char *last_annotation_string = NULL;
|
|
||||||
const void *last_annotation_ir = NULL;
|
|
||||||
|
|
||||||
if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
|
if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
|
||||||
if (prog) {
|
if (prog) {
|
||||||
fprintf(stderr,
|
fprintf(stderr,
|
||||||
|
@ -914,46 +911,8 @@ gen8_fs_generator::generate_code(exec_list *instructions)
|
||||||
fs_inst *ir = (fs_inst *) node;
|
fs_inst *ir = (fs_inst *) node;
|
||||||
struct brw_reg src[3], dst;
|
struct brw_reg src[3], dst;
|
||||||
|
|
||||||
if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
|
if (unlikely(INTEL_DEBUG & DEBUG_WM))
|
||||||
foreach_list(node, &cfg->block_list) {
|
annotate(brw, annotation, cfg, ir, next_inst_offset);
|
||||||
bblock_link *link = (bblock_link *)node;
|
|
||||||
bblock_t *block = link->block;
|
|
||||||
|
|
||||||
if (block->start == ir) {
|
|
||||||
fprintf(stderr, " START B%d", block->block_num);
|
|
||||||
foreach_list(predecessor_node, &block->parents) {
|
|
||||||
bblock_link *predecessor_link =
|
|
||||||
(bblock_link *)predecessor_node;
|
|
||||||
bblock_t *predecessor_block = predecessor_link->block;
|
|
||||||
fprintf(stderr, " <-B%d", predecessor_block->block_num);
|
|
||||||
}
|
|
||||||
fprintf(stderr, "\n");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
if (last_annotation_ir != ir->ir) {
|
|
||||||
last_annotation_ir = ir->ir;
|
|
||||||
if (last_annotation_ir) {
|
|
||||||
fprintf(stderr, " ");
|
|
||||||
if (prog) {
|
|
||||||
((ir_instruction *) ir->ir)->fprint(stderr);
|
|
||||||
} else if (prog) {
|
|
||||||
const prog_instruction *fpi;
|
|
||||||
fpi = (const prog_instruction *) ir->ir;
|
|
||||||
fprintf(stderr, "%d: ", (int)(fpi - prog->Instructions));
|
|
||||||
_mesa_fprint_instruction_opt(stderr,
|
|
||||||
fpi,
|
|
||||||
0, PROG_PRINT_DEBUG, NULL);
|
|
||||||
}
|
|
||||||
fprintf(stderr, "\n");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (last_annotation_string != ir->annotation) {
|
|
||||||
last_annotation_string = ir->annotation;
|
|
||||||
if (last_annotation_string)
|
|
||||||
fprintf(stderr, " %s\n", last_annotation_string);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
for (unsigned int i = 0; i < 3; i++) {
|
for (unsigned int i = 0; i < 3; i++) {
|
||||||
src[i] = brw_reg_from_fs_reg(&ir->src[i]);
|
src[i] = brw_reg_from_fs_reg(&ir->src[i]);
|
||||||
|
@ -1296,44 +1255,10 @@ gen8_fs_generator::generate_code(exec_list *instructions)
|
||||||
}
|
}
|
||||||
abort();
|
abort();
|
||||||
}
|
}
|
||||||
|
|
||||||
if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
|
|
||||||
gen8_disassemble(brw, store, last_native_inst_offset, next_inst_offset, stderr);
|
|
||||||
|
|
||||||
foreach_list(node, &cfg->block_list) {
|
|
||||||
bblock_link *link = (bblock_link *)node;
|
|
||||||
bblock_t *block = link->block;
|
|
||||||
|
|
||||||
if (block->end == ir) {
|
|
||||||
fprintf(stderr, " END B%d", block->block_num);
|
|
||||||
foreach_list(successor_node, &block->children) {
|
|
||||||
bblock_link *successor_link =
|
|
||||||
(bblock_link *)successor_node;
|
|
||||||
bblock_t *successor_block = successor_link->block;
|
|
||||||
fprintf(stderr, " ->B%d", successor_block->block_num);
|
|
||||||
}
|
|
||||||
fprintf(stderr, "\n");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
last_native_inst_offset = next_inst_offset;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
|
|
||||||
fprintf(stderr, "\n");
|
|
||||||
}
|
}
|
||||||
|
|
||||||
patch_jump_targets();
|
patch_jump_targets();
|
||||||
|
annotation_finalize(annotation, next_inst_offset);
|
||||||
/* OK, while the INTEL_DEBUG=fs above is very nice for debugging FS
|
|
||||||
* emit issues, it doesn't get the jump distances into the output,
|
|
||||||
* which is often something we want to debug. So this is here in
|
|
||||||
* case you're doing that.
|
|
||||||
*/
|
|
||||||
if (0 && unlikely(INTEL_DEBUG & DEBUG_WM)) {
|
|
||||||
gen8_disassemble(brw, store, 0, next_inst_offset, stderr);
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
const unsigned *
|
const unsigned *
|
||||||
|
@ -1344,8 +1269,17 @@ gen8_fs_generator::generate_assembly(exec_list *simd8_instructions,
|
||||||
assert(simd8_instructions || simd16_instructions);
|
assert(simd8_instructions || simd16_instructions);
|
||||||
|
|
||||||
if (simd8_instructions) {
|
if (simd8_instructions) {
|
||||||
|
struct annotation_info annotation;
|
||||||
|
memset(&annotation, 0, sizeof(annotation));
|
||||||
|
|
||||||
dispatch_width = 8;
|
dispatch_width = 8;
|
||||||
generate_code(simd8_instructions);
|
generate_code(simd8_instructions, &annotation);
|
||||||
|
|
||||||
|
if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
|
||||||
|
dump_assembly(store, annotation.ann_count, annotation.ann, brw, prog,
|
||||||
|
gen8_disassemble);
|
||||||
|
ralloc_free(annotation.ann);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
if (simd16_instructions) {
|
if (simd16_instructions) {
|
||||||
|
@ -1356,8 +1290,17 @@ gen8_fs_generator::generate_assembly(exec_list *simd8_instructions,
|
||||||
/* Save off the start of this SIMD16 program */
|
/* Save off the start of this SIMD16 program */
|
||||||
prog_data->prog_offset_16 = nr_inst * sizeof(gen8_instruction);
|
prog_data->prog_offset_16 = nr_inst * sizeof(gen8_instruction);
|
||||||
|
|
||||||
|
struct annotation_info annotation;
|
||||||
|
memset(&annotation, 0, sizeof(annotation));
|
||||||
|
|
||||||
dispatch_width = 16;
|
dispatch_width = 16;
|
||||||
generate_code(simd16_instructions);
|
generate_code(simd16_instructions, &annotation);
|
||||||
|
|
||||||
|
if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
|
||||||
|
dump_assembly(store, annotation.ann_count, annotation.ann,
|
||||||
|
brw, prog, gen8_disassemble);
|
||||||
|
ralloc_free(annotation.ann);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
*assembly_size = next_inst_offset;
|
*assembly_size = next_inst_offset;
|
||||||
|
|
|
@ -22,6 +22,7 @@
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include "brw_vec4.h"
|
#include "brw_vec4.h"
|
||||||
|
#include "brw_cfg.h"
|
||||||
|
|
||||||
extern "C" {
|
extern "C" {
|
||||||
#include "brw_eu.h"
|
#include "brw_eu.h"
|
||||||
|
@ -841,12 +842,9 @@ gen8_vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
gen8_vec4_generator::generate_code(exec_list *instructions)
|
gen8_vec4_generator::generate_code(exec_list *instructions,
|
||||||
|
struct annotation_info *annotation)
|
||||||
{
|
{
|
||||||
int last_native_inst_offset = 0;
|
|
||||||
const char *last_annotation_string = NULL;
|
|
||||||
const void *last_annotation_ir = NULL;
|
|
||||||
|
|
||||||
if (unlikely(debug_flag)) {
|
if (unlikely(debug_flag)) {
|
||||||
if (shader_prog) {
|
if (shader_prog) {
|
||||||
fprintf(stderr, "Native code for %s vertex shader %d:\n",
|
fprintf(stderr, "Native code for %s vertex shader %d:\n",
|
||||||
|
@ -857,33 +855,16 @@ gen8_vec4_generator::generate_code(exec_list *instructions)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
cfg_t *cfg = NULL;
|
||||||
|
if (unlikely(debug_flag))
|
||||||
|
cfg = new(mem_ctx) cfg_t(instructions);
|
||||||
|
|
||||||
foreach_list(node, instructions) {
|
foreach_list(node, instructions) {
|
||||||
vec4_instruction *ir = (vec4_instruction *) node;
|
vec4_instruction *ir = (vec4_instruction *) node;
|
||||||
struct brw_reg src[3], dst;
|
struct brw_reg src[3], dst;
|
||||||
|
|
||||||
if (unlikely(debug_flag)) {
|
if (unlikely(debug_flag))
|
||||||
if (last_annotation_ir != ir->ir) {
|
annotate(brw, annotation, cfg, ir, next_inst_offset);
|
||||||
last_annotation_ir = ir->ir;
|
|
||||||
if (last_annotation_ir) {
|
|
||||||
fprintf(stderr, " ");
|
|
||||||
if (shader_prog) {
|
|
||||||
((ir_instruction *) last_annotation_ir)->fprint(stderr);
|
|
||||||
} else {
|
|
||||||
const prog_instruction *vpi;
|
|
||||||
vpi = (const prog_instruction *) ir->ir;
|
|
||||||
fprintf(stderr, "%d: ", (int)(vpi - prog->Instructions));
|
|
||||||
_mesa_fprint_instruction_opt(stderr, vpi, 0,
|
|
||||||
PROG_PRINT_DEBUG, NULL);
|
|
||||||
}
|
|
||||||
fprintf(stderr, "\n");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (last_annotation_string != ir->annotation) {
|
|
||||||
last_annotation_string = ir->annotation;
|
|
||||||
if (last_annotation_string)
|
|
||||||
fprintf(stderr, " %s\n", last_annotation_string);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
for (unsigned int i = 0; i < 3; i++) {
|
for (unsigned int i = 0; i < 3; i++) {
|
||||||
src[i] = ir->get_src(prog_data, i);
|
src[i] = ir->get_src(prog_data, i);
|
||||||
|
@ -908,37 +889,29 @@ gen8_vec4_generator::generate_code(exec_list *instructions)
|
||||||
gen8_set_no_dd_clear(last, ir->no_dd_clear);
|
gen8_set_no_dd_clear(last, ir->no_dd_clear);
|
||||||
gen8_set_no_dd_check(last, ir->no_dd_check);
|
gen8_set_no_dd_check(last, ir->no_dd_check);
|
||||||
}
|
}
|
||||||
|
|
||||||
if (unlikely(debug_flag)) {
|
|
||||||
gen8_disassemble(brw, store, last_native_inst_offset, next_inst_offset, stderr);
|
|
||||||
}
|
|
||||||
|
|
||||||
last_native_inst_offset = next_inst_offset;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (unlikely(debug_flag)) {
|
|
||||||
fprintf(stderr, "\n");
|
|
||||||
}
|
}
|
||||||
|
|
||||||
patch_jump_targets();
|
patch_jump_targets();
|
||||||
|
annotation_finalize(annotation, next_inst_offset);
|
||||||
/* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS
|
|
||||||
* emit issues, it doesn't get the jump distances into the output,
|
|
||||||
* which is often something we want to debug. So this is here in
|
|
||||||
* case you're doing that.
|
|
||||||
*/
|
|
||||||
if (0 && unlikely(debug_flag)) {
|
|
||||||
gen8_disassemble(brw, store, 0, next_inst_offset, stderr);
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
const unsigned *
|
const unsigned *
|
||||||
gen8_vec4_generator::generate_assembly(exec_list *instructions,
|
gen8_vec4_generator::generate_assembly(exec_list *instructions,
|
||||||
unsigned *assembly_size)
|
unsigned *assembly_size)
|
||||||
{
|
{
|
||||||
|
struct annotation_info annotation;
|
||||||
|
memset(&annotation, 0, sizeof(annotation));
|
||||||
|
|
||||||
default_state.access_mode = BRW_ALIGN_16;
|
default_state.access_mode = BRW_ALIGN_16;
|
||||||
default_state.exec_size = BRW_EXECUTE_8;
|
default_state.exec_size = BRW_EXECUTE_8;
|
||||||
generate_code(instructions);
|
generate_code(instructions, &annotation);
|
||||||
|
|
||||||
|
if (unlikely(debug_flag)) {
|
||||||
|
dump_assembly(store, annotation.ann_count, annotation.ann,
|
||||||
|
brw, prog, gen8_disassemble);
|
||||||
|
ralloc_free(annotation.ann);
|
||||||
|
}
|
||||||
|
|
||||||
*assembly_size = next_inst_offset;
|
*assembly_size = next_inst_offset;
|
||||||
return (const unsigned *) store;
|
return (const unsigned *) store;
|
||||||
}
|
}
|
||||||
|
|
|
@ -24,6 +24,10 @@
|
||||||
#ifndef _INTEL_ASM_ANNOTATION_H
|
#ifndef _INTEL_ASM_ANNOTATION_H
|
||||||
#define _INTEL_ASM_ANNOTATION_H
|
#define _INTEL_ASM_ANNOTATION_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
struct bblock_t;
|
struct bblock_t;
|
||||||
struct brw_context;
|
struct brw_context;
|
||||||
struct gl_program;
|
struct gl_program;
|
||||||
|
@ -42,6 +46,16 @@ struct annotation {
|
||||||
const char *annotation;
|
const char *annotation;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
struct annotation_info {
|
||||||
|
void *mem_ctx;
|
||||||
|
struct annotation *ann;
|
||||||
|
int ann_count;
|
||||||
|
int ann_size;
|
||||||
|
|
||||||
|
/** Block index in the cfg. */
|
||||||
|
int cur_block;
|
||||||
|
};
|
||||||
|
|
||||||
typedef void (*disassemble_func)(struct brw_context *brw, void *assembly,
|
typedef void (*disassemble_func)(struct brw_context *brw, void *assembly,
|
||||||
int start, int end, FILE *out);
|
int start, int end, FILE *out);
|
||||||
|
|
||||||
|
@ -50,4 +64,8 @@ dump_assembly(void *assembly, int num_annotations, struct annotation *annotation
|
||||||
struct brw_context *brw, const struct gl_program *prog,
|
struct brw_context *brw, const struct gl_program *prog,
|
||||||
disassemble_func disassemble);
|
disassemble_func disassemble);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
} /* extern "C" */
|
||||||
|
#endif
|
||||||
|
|
||||||
#endif /* _INTEL_ASM_ANNOTATION_H */
|
#endif /* _INTEL_ASM_ANNOTATION_H */
|
||||||
|
|
Loading…
Reference in New Issue