nir,amd: Suffix nir_op_cube_face_coord/index with _amd
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11463>
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@ -2031,7 +2031,7 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
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}
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break;
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}
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case nir_op_cube_face_coord: {
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case nir_op_cube_face_coord_amd: {
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Temp in = get_alu_src(ctx, instr->src[0], 3);
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Temp src[3] = { emit_extract_vector(ctx, in, 0, v1),
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emit_extract_vector(ctx, in, 1, v1),
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@ -2049,7 +2049,7 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
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bld.pseudo(aco_opcode::p_create_vector, Definition(dst), sc, tc);
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break;
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}
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case nir_op_cube_face_index: {
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case nir_op_cube_face_index_amd: {
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Temp in = get_alu_src(ctx, instr->src[0], 3);
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Temp src[3] = { emit_extract_vector(ctx, in, 0, v1),
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emit_extract_vector(ctx, in, 1, v1),
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@ -704,8 +704,8 @@ void init_context(isel_context *ctx, nir_shader *shader)
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case nir_op_ldexp:
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case nir_op_frexp_sig:
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case nir_op_frexp_exp:
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case nir_op_cube_face_index:
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case nir_op_cube_face_coord:
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case nir_op_cube_face_index_amd:
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case nir_op_cube_face_coord_amd:
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case nir_op_sad_u8x4:
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type = RegType::vgpr;
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break;
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@ -578,8 +578,8 @@ static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
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case nir_op_unpack_half_2x16:
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src_components = 1;
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break;
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case nir_op_cube_face_coord:
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case nir_op_cube_face_index:
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case nir_op_cube_face_coord_amd:
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case nir_op_cube_face_index_amd:
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src_components = 3;
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break;
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case nir_op_pack_64_4x16:
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@ -1180,7 +1180,7 @@ static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
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break;
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}
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case nir_op_cube_face_coord: {
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case nir_op_cube_face_coord_amd: {
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src[0] = ac_to_float(&ctx->ac, src[0]);
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LLVMValueRef results[2];
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LLVMValueRef in[3];
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@ -1201,7 +1201,7 @@ static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
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break;
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}
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case nir_op_cube_face_index: {
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case nir_op_cube_face_index_amd: {
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src[0] = ac_to_float(&ctx->ac, src[0]);
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LLVMValueRef in[3];
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for (unsigned chan = 0; chan < 3; chan++)
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@ -125,8 +125,8 @@ lower_alu_instr_scalar(nir_builder *b, nir_instr *instr, void *_data)
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case nir_op_vec4:
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case nir_op_vec3:
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case nir_op_vec2:
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case nir_op_cube_face_coord:
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case nir_op_cube_face_index:
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case nir_op_cube_face_coord_amd:
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case nir_op_cube_face_index_amd:
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/* We don't need to scalarize these ops, they're the ones generated to
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* group up outputs into a value that can be SSAed.
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*/
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@ -514,7 +514,7 @@ for (unsigned bit = 0; bit < bit_size; bit++) {
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""")
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# AMD_gcn_shader extended instructions
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unop_horiz("cube_face_coord", 2, tfloat32, 3, tfloat32, """
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unop_horiz("cube_face_coord_amd", 2, tfloat32, 3, tfloat32, """
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dst.x = dst.y = 0.0;
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float absX = fabsf(src0.x);
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float absY = fabsf(src0.y);
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@ -536,7 +536,7 @@ dst.x = dst.x * (1.0f / ma) + 0.5f;
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dst.y = dst.y * (1.0f / ma) + 0.5f;
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""")
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unop_horiz("cube_face_index", 1, tfloat32, 3, tfloat32, """
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unop_horiz("cube_face_index_amd", 1, tfloat32, 3, tfloat32, """
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float absX = fabsf(src0.x);
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float absY = fabsf(src0.y);
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float absZ = fabsf(src0.z);
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@ -33,10 +33,10 @@ vtn_handle_amd_gcn_shader_instruction(struct vtn_builder *b, SpvOp ext_opcode,
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nir_ssa_def *def;
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switch ((enum GcnShaderAMD)ext_opcode) {
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case CubeFaceIndexAMD:
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def = nir_cube_face_index(&b->nb, vtn_get_nir_ssa(b, w[5]));
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def = nir_cube_face_index_amd(&b->nb, vtn_get_nir_ssa(b, w[5]));
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break;
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case CubeFaceCoordAMD:
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def = nir_cube_face_coord(&b->nb, vtn_get_nir_ssa(b, w[5]));
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def = nir_cube_face_coord_amd(&b->nb, vtn_get_nir_ssa(b, w[5]));
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break;
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case TimeAMD: {
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def = nir_pack_64_2x32(&b->nb, nir_shader_clock(&b->nb, NIR_SCOPE_SUBGROUP));
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@ -997,8 +997,8 @@ static void visit_alu(struct lp_build_nir_context *bld_base, const nir_alu_instr
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case nir_op_unpack_half_2x16:
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src_components = 1;
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break;
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case nir_op_cube_face_coord:
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case nir_op_cube_face_index:
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case nir_op_cube_face_coord_amd:
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case nir_op_cube_face_index_amd:
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src_components = 3;
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break;
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case nir_op_fsum2:
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