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nir,amd: Suffix nir_op_cube_face_coord/index with _amd 

Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11463>
This commit is contained in:
Jason Ekstrand 2021-06-18 09:17:01 -05:00
parent e5510536e7
commit f0f713960b
7 changed files with 16 additions and 16 deletions
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4
src/amd/compiler/aco_instruction_selection.cpp
View File

@ -2031,7 +2031,7 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
}
break;
}
case nir_op_cube_face_coord: {
case nir_op_cube_face_coord_amd: {
Temp in = get_alu_src(ctx, instr->src[0], 3);
Temp src[3] = { emit_extract_vector(ctx, in, 0, v1),
emit_extract_vector(ctx, in, 1, v1),
@ -2049,7 +2049,7 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
bld.pseudo(aco_opcode::p_create_vector, Definition(dst), sc, tc);
break;
}
case nir_op_cube_face_index: {
case nir_op_cube_face_index_amd: {
Temp in = get_alu_src(ctx, instr->src[0], 3);
Temp src[3] = { emit_extract_vector(ctx, in, 0, v1),
emit_extract_vector(ctx, in, 1, v1),

4
src/amd/compiler/aco_instruction_selection_setup.cpp
View File

@ -704,8 +704,8 @@ void init_context(isel_context *ctx, nir_shader *shader)
case nir_op_ldexp:
case nir_op_frexp_sig:
case nir_op_frexp_exp:
case nir_op_cube_face_index:
case nir_op_cube_face_coord:
case nir_op_cube_face_index_amd:
case nir_op_cube_face_coord_amd:
case nir_op_sad_u8x4:
type = RegType::vgpr;
break;

8
src/amd/llvm/ac_nir_to_llvm.c
View File

@ -578,8 +578,8 @@ static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
case nir_op_unpack_half_2x16:
src_components = 1;
break;
case nir_op_cube_face_coord:
case nir_op_cube_face_index:
case nir_op_cube_face_coord_amd:
case nir_op_cube_face_index_amd:
src_components = 3;
break;
case nir_op_pack_64_4x16:
@ -1180,7 +1180,7 @@ static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
break;
}
case nir_op_cube_face_coord: {
case nir_op_cube_face_coord_amd: {
src[0] = ac_to_float(&ctx->ac, src[0]);
LLVMValueRef results[2];
LLVMValueRef in[3];
@ -1201,7 +1201,7 @@ static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
break;
}
case nir_op_cube_face_index: {
case nir_op_cube_face_index_amd: {
src[0] = ac_to_float(&ctx->ac, src[0]);
LLVMValueRef in[3];
for (unsigned chan = 0; chan < 3; chan++)

4
src/compiler/nir/nir_lower_alu_to_scalar.c
View File

@ -125,8 +125,8 @@ lower_alu_instr_scalar(nir_builder *b, nir_instr *instr, void *_data)
case nir_op_vec4:
case nir_op_vec3:
case nir_op_vec2:
case nir_op_cube_face_coord:
case nir_op_cube_face_index:
case nir_op_cube_face_coord_amd:
case nir_op_cube_face_index_amd:
/* We don't need to scalarize these ops, they're the ones generated to
* group up outputs into a value that can be SSAed.
*/

4
src/compiler/nir/nir_opcodes.py
View File

@ -514,7 +514,7 @@ for (unsigned bit = 0; bit < bit_size; bit++) {
""")
# AMD_gcn_shader extended instructions
unop_horiz("cube_face_coord", 2, tfloat32, 3, tfloat32, """
unop_horiz("cube_face_coord_amd", 2, tfloat32, 3, tfloat32, """
dst.x = dst.y = 0.0;
float absX = fabsf(src0.x);
float absY = fabsf(src0.y);
@ -536,7 +536,7 @@ dst.x = dst.x * (1.0f / ma) + 0.5f;
dst.y = dst.y * (1.0f / ma) + 0.5f;
""")
unop_horiz("cube_face_index", 1, tfloat32, 3, tfloat32, """
unop_horiz("cube_face_index_amd", 1, tfloat32, 3, tfloat32, """
float absX = fabsf(src0.x);
float absY = fabsf(src0.y);
float absZ = fabsf(src0.z);

4
src/compiler/spirv/vtn_amd.c
View File

@ -33,10 +33,10 @@ vtn_handle_amd_gcn_shader_instruction(struct vtn_builder *b, SpvOp ext_opcode,
nir_ssa_def *def;
switch ((enum GcnShaderAMD)ext_opcode) {
case CubeFaceIndexAMD:
def = nir_cube_face_index(&b->nb, vtn_get_nir_ssa(b, w[5]));
def = nir_cube_face_index_amd(&b->nb, vtn_get_nir_ssa(b, w[5]));
break;
case CubeFaceCoordAMD:
def = nir_cube_face_coord(&b->nb, vtn_get_nir_ssa(b, w[5]));
def = nir_cube_face_coord_amd(&b->nb, vtn_get_nir_ssa(b, w[5]));
break;
case TimeAMD: {
def = nir_pack_64_2x32(&b->nb, nir_shader_clock(&b->nb, NIR_SCOPE_SUBGROUP));

4
src/gallium/auxiliary/gallivm/lp_bld_nir.c
View File

@ -997,8 +997,8 @@ static void visit_alu(struct lp_build_nir_context *bld_base, const nir_alu_instr
case nir_op_unpack_half_2x16:
src_components = 1;
break;
case nir_op_cube_face_coord:
case nir_op_cube_face_index:
case nir_op_cube_face_coord_amd:
case nir_op_cube_face_index_amd:
src_components = 3;
break;
case nir_op_fsum2: