amd/common:add uvd hevc enc support check in hw query
Based on amdgpu hardware query information to check if UVD hevc enc support Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
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@ -98,7 +98,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
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{
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struct amdgpu_buffer_size_alignments alignment_info = {};
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struct amdgpu_heap_info vram, vram_vis, gtt;
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struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {}, vce = {}, vcn_dec = {}, vcn_enc = {};
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struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {}, uvd_enc = {}, vce = {}, vcn_dec = {}, vcn_enc = {};
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uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0;
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int r, i, j;
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drmDevicePtr devinfo;
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@ -166,6 +166,14 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
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return false;
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}
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if (info->drm_major == 3 && info->drm_minor >= 17) {
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r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD_ENC, 0, &uvd_enc);
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if (r) {
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fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd_enc) failed.\n");
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return false;
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}
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}
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if (info->drm_major == 3 && info->drm_minor >= 17) {
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r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_DEC, 0, &vcn_dec);
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if (r) {
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@ -281,6 +289,8 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
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uvd.available_rings ? uvd_version : 0;
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info->vce_fw_version =
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vce.available_rings ? vce_version : 0;
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info->uvd_enc_supported =
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uvd_enc.available_rings ? true : false;
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info->has_userptr = true;
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info->has_syncobj = has_syncobj(fd);
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info->has_syncobj_wait_for_submit = info->has_syncobj && info->drm_minor >= 20;
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@ -66,6 +66,7 @@ struct radeon_info {
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uint32_t num_compute_rings;
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uint32_t uvd_fw_version;
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uint32_t vce_fw_version;
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bool uvd_enc_supported;
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uint32_t me_fw_version;
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uint32_t me_fw_feature;
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uint32_t pfp_fw_version;
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