radeonsi: merge sampler and image descriptor lists into one
Sampler slots: slot[8], .. slot[39] (ascending) Image slots: slot[7], .. slot[0] (descending) Each image occupies 1/2 of each slot, so there are 16 images in total, therefore the layout is: slot[15], .. slot[0]. (in 1/2 slot increments) Updating image slot 2n+i (i <= 1) also dirties and re-uploads slot 2n+!i. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák
parent
5df24c3fa6
commit
f07c15ef80
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@ -99,17 +99,14 @@ static void si_init_descriptors(struct si_descriptors *desc,
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unsigned shader_userdata_index,
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unsigned element_dw_size,
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unsigned num_elements,
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const uint32_t *null_descriptor,
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unsigned *ce_offset)
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{
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int i;
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assert(num_elements <= sizeof(desc->dirty_mask)*8);
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desc->list = CALLOC(num_elements, element_dw_size * 4);
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desc->element_dw_size = element_dw_size;
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desc->num_elements = num_elements;
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desc->dirty_mask = num_elements == 32 ? ~0u : (1u << num_elements) - 1;
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desc->dirty_mask = u_bit_consecutive64(0, num_elements);
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desc->shader_userdata_offset = shader_userdata_index * 4;
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if (ce_offset) {
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@ -119,14 +116,6 @@ static void si_init_descriptors(struct si_descriptors *desc,
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/* make sure that ce_offset stays 32 byte aligned */
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*ce_offset += align(element_dw_size * num_elements * 4, 32);
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}
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/* Initialize the array to NULL descriptors if the element size is 8. */
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if (null_descriptor) {
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assert(element_dw_size % 8 == 0);
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for (i = 0; i < num_elements * element_dw_size / 8; i++)
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memcpy(desc->list + i * 8, null_descriptor,
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8 * 4);
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}
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}
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static void si_release_descriptors(struct si_descriptors *desc)
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@ -219,8 +208,8 @@ static bool si_upload_descriptors(struct si_context *sctx,
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while(desc->dirty_mask) {
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int begin, count;
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u_bit_scan_consecutive_range(&desc->dirty_mask, &begin,
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&count);
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u_bit_scan_consecutive_range64(&desc->dirty_mask, &begin,
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&count);
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begin *= desc->element_dw_size;
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count *= desc->element_dw_size;
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@ -273,16 +262,16 @@ si_descriptors_begin_new_cs(struct si_context *sctx, struct si_descriptors *desc
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/* SAMPLER VIEWS */
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static unsigned
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si_sampler_descriptors_idx(unsigned shader)
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si_sampler_and_image_descriptors_idx(unsigned shader)
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{
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return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
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SI_SHADER_DESCS_SAMPLERS;
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SI_SHADER_DESCS_SAMPLERS_AND_IMAGES;
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}
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static struct si_descriptors *
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si_sampler_descriptors(struct si_context *sctx, unsigned shader)
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si_sampler_and_image_descriptors(struct si_context *sctx, unsigned shader)
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{
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return &sctx->descriptors[si_sampler_descriptors_idx(shader)];
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return &sctx->descriptors[si_sampler_and_image_descriptors_idx(shader)];
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}
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static void si_release_sampler_views(struct si_sampler_views *views)
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@ -474,8 +463,9 @@ static void si_set_sampler_view(struct si_context *sctx,
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{
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struct si_sampler_views *views = &sctx->samplers[shader].views;
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struct si_sampler_view *rview = (struct si_sampler_view*)view;
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struct si_descriptors *descs = si_sampler_descriptors(sctx, shader);
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uint32_t *desc = descs->list + slot * 16;
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struct si_descriptors *descs = si_sampler_and_image_descriptors(sctx, shader);
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unsigned desc_slot = si_get_sampler_slot(slot);
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uint32_t *desc = descs->list + desc_slot * 16;
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if (views->views[slot] == view && !disallow_early_out)
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return;
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@ -549,8 +539,8 @@ static void si_set_sampler_view(struct si_context *sctx,
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views->enabled_mask &= ~(1u << slot);
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}
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descs->dirty_mask |= 1u << slot;
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sctx->descriptors_dirty |= 1u << si_sampler_descriptors_idx(shader);
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descs->dirty_mask |= 1ull << desc_slot;
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sctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
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}
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static bool is_compressed_colortex(struct r600_texture *rtex)
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@ -656,19 +646,6 @@ si_samplers_update_compressed_colortex_mask(struct si_textures_info *samplers)
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/* IMAGE VIEWS */
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static unsigned
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si_image_descriptors_idx(unsigned shader)
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{
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return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
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SI_SHADER_DESCS_IMAGES;
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}
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static struct si_descriptors*
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si_image_descriptors(struct si_context *sctx, unsigned shader)
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{
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return &sctx->descriptors[si_image_descriptors_idx(shader)];
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}
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static void
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si_release_image_views(struct si_images_info *images)
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{
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@ -704,15 +681,17 @@ si_disable_shader_image(struct si_context *ctx, unsigned shader, unsigned slot)
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struct si_images_info *images = &ctx->images[shader];
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if (images->enabled_mask & (1u << slot)) {
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struct si_descriptors *descs = si_image_descriptors(ctx, shader);
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struct si_descriptors *descs = si_sampler_and_image_descriptors(ctx, shader);
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unsigned desc_slot = si_get_image_slot(slot);
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pipe_resource_reference(&images->views[slot].resource, NULL);
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images->compressed_colortex_mask &= ~(1 << slot);
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memcpy(descs->list + slot*8, null_image_descriptor, 8*4);
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memcpy(descs->list + desc_slot*8, null_image_descriptor, 8*4);
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images->enabled_mask &= ~(1u << slot);
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descs->dirty_mask |= 1u << slot;
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ctx->descriptors_dirty |= 1u << si_image_descriptors_idx(shader);
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/* two 8-byte images share one 16-byte slot */
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descs->dirty_mask |= 1u << (desc_slot / 2);
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ctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
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}
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}
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@ -735,9 +714,10 @@ static void si_set_shader_image(struct si_context *ctx,
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{
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struct si_screen *screen = ctx->screen;
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struct si_images_info *images = &ctx->images[shader];
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struct si_descriptors *descs = si_image_descriptors(ctx, shader);
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struct si_descriptors *descs = si_sampler_and_image_descriptors(ctx, shader);
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struct r600_resource *res;
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uint32_t *desc = descs->list + slot * 8;
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unsigned desc_slot = si_get_image_slot(slot);
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uint32_t *desc = descs->list + desc_slot * 8;
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if (!view || !view->resource) {
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si_disable_shader_image(ctx, shader, slot);
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@ -831,8 +811,9 @@ static void si_set_shader_image(struct si_context *ctx,
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}
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images->enabled_mask |= 1u << slot;
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descs->dirty_mask |= 1u << slot;
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ctx->descriptors_dirty |= 1u << si_image_descriptors_idx(shader);
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/* two 8-byte images share one 16-byte slot */
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descs->dirty_mask |= 1u << (desc_slot / 2);
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ctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
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/* Since this can flush, it must be done after enabled_mask is updated. */
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si_sampler_view_add_buffer(ctx, &res->b.b,
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@ -895,7 +876,7 @@ static void si_bind_sampler_states(struct pipe_context *ctx,
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{
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struct si_context *sctx = (struct si_context *)ctx;
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struct si_textures_info *samplers = &sctx->samplers[shader];
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struct si_descriptors *desc = si_sampler_descriptors(sctx, shader);
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struct si_descriptors *desc = si_sampler_and_image_descriptors(sctx, shader);
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struct si_sampler_state **sstates = (struct si_sampler_state**)states;
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int i;
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@ -904,6 +885,7 @@ static void si_bind_sampler_states(struct pipe_context *ctx,
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for (i = 0; i < count; i++) {
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unsigned slot = start + i;
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unsigned desc_slot = si_get_sampler_slot(slot);
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if (!sstates[i] ||
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sstates[i] == samplers->views.sampler_states[slot])
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@ -923,9 +905,9 @@ static void si_bind_sampler_states(struct pipe_context *ctx,
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((struct r600_texture*)samplers->views.views[slot]->texture)->fmask.size)
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continue;
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memcpy(desc->list + slot * 16 + 12, sstates[i]->val, 4*4);
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desc->dirty_mask |= 1u << slot;
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sctx->descriptors_dirty |= 1u << si_sampler_descriptors_idx(shader);
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memcpy(desc->list + desc_slot * 16 + 12, sstates[i]->val, 4*4);
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desc->dirty_mask |= 1ull << desc_slot;
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sctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
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}
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}
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@ -948,7 +930,7 @@ static void si_init_buffer_resources(struct si_buffer_resources *buffers,
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buffers->buffers = CALLOC(num_buffers, sizeof(struct pipe_resource*));
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si_init_descriptors(descs, shader_userdata_index, 4,
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num_buffers, NULL, ce_offset);
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num_buffers, ce_offset);
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}
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static void si_release_buffer_resources(struct si_buffer_resources *buffers,
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@ -1711,19 +1693,21 @@ static void si_rebind_buffer(struct pipe_context *ctx, struct pipe_resource *buf
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for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
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struct si_sampler_views *views = &sctx->samplers[shader].views;
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struct si_descriptors *descs =
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si_sampler_descriptors(sctx, shader);
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si_sampler_and_image_descriptors(sctx, shader);
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unsigned mask = views->enabled_mask;
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while (mask) {
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unsigned i = u_bit_scan(&mask);
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if (views->views[i]->texture == buf) {
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unsigned desc_slot = si_get_sampler_slot(i);
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si_desc_reset_buffer_offset(ctx,
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descs->list +
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i * 16 + 4,
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desc_slot * 16 + 4,
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old_va, buf);
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descs->dirty_mask |= 1u << i;
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descs->dirty_mask |= 1ull << desc_slot;
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sctx->descriptors_dirty |=
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1u << si_sampler_descriptors_idx(shader);
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1u << si_sampler_and_image_descriptors_idx(shader);
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radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
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rbuffer, RADEON_USAGE_READ,
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@ -1739,22 +1723,25 @@ static void si_rebind_buffer(struct pipe_context *ctx, struct pipe_resource *buf
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for (shader = 0; shader < SI_NUM_SHADERS; ++shader) {
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struct si_images_info *images = &sctx->images[shader];
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struct si_descriptors *descs =
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si_image_descriptors(sctx, shader);
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si_sampler_and_image_descriptors(sctx, shader);
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unsigned mask = images->enabled_mask;
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while (mask) {
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unsigned i = u_bit_scan(&mask);
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if (images->views[i].resource == buf) {
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unsigned desc_slot = si_get_image_slot(i);
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if (images->views[i].access & PIPE_IMAGE_ACCESS_WRITE)
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si_mark_image_range_valid(&images->views[i]);
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si_desc_reset_buffer_offset(
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ctx, descs->list + i * 8 + 4,
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ctx, descs->list + desc_slot * 8 + 4,
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old_va, buf);
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descs->dirty_mask |= 1u << i;
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/* two 8-byte images share one 16-byte slot */
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descs->dirty_mask |= 1u << (desc_slot / 2);
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sctx->descriptors_dirty |=
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1u << si_image_descriptors_idx(shader);
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1u << si_sampler_and_image_descriptors_idx(shader);
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radeon_add_to_buffer_list_check_mem(
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&sctx->b, &sctx->b.gfx, rbuffer,
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@ -2016,12 +2003,11 @@ void si_init_all_descriptors(struct si_context *sctx)
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* Rarely used descriptors don't use CE RAM.
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*/
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bool big_ce = sctx->b.chip_class <= VI;
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bool images_use_ce = big_ce;
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bool const_and_shaderbufs_use_ce = big_ce ||
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i == PIPE_SHADER_VERTEX ||
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i == PIPE_SHADER_FRAGMENT;
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bool samplers_use_ce = big_ce ||
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i == PIPE_SHADER_FRAGMENT;
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bool samplers_and_images_use_ce = big_ce ||
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i == PIPE_SHADER_FRAGMENT;
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si_init_buffer_resources(&sctx->const_and_shader_buffers[i],
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si_const_and_shader_buffer_descriptors(sctx, i),
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@ -2035,21 +2021,19 @@ void si_init_all_descriptors(struct si_context *sctx)
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RADEON_PRIO_CONST_BUFFER,
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const_and_shaderbufs_use_ce ? &ce_offset : NULL);
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si_init_descriptors(si_sampler_descriptors(sctx, i),
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gfx9_tcs ? GFX9_SGPR_TCS_SAMPLERS :
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gfx9_gs ? GFX9_SGPR_GS_SAMPLERS :
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SI_SGPR_SAMPLERS,
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16, SI_NUM_SAMPLERS,
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null_texture_descriptor,
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samplers_use_ce ? &ce_offset : NULL);
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struct si_descriptors *desc = si_sampler_and_image_descriptors(sctx, i);
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si_init_descriptors(desc,
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gfx9_tcs ? GFX9_SGPR_TCS_SAMPLERS_AND_IMAGES :
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gfx9_gs ? GFX9_SGPR_GS_SAMPLERS_AND_IMAGES :
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SI_SGPR_SAMPLERS_AND_IMAGES,
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16, SI_NUM_IMAGES / 2 + SI_NUM_SAMPLERS,
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samplers_and_images_use_ce ? &ce_offset : NULL);
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si_init_descriptors(si_image_descriptors(sctx, i),
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gfx9_tcs ? GFX9_SGPR_TCS_IMAGES :
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gfx9_gs ? GFX9_SGPR_GS_IMAGES :
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SI_SGPR_IMAGES,
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8, SI_NUM_IMAGES,
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null_image_descriptor,
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images_use_ce ? &ce_offset : NULL);
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int j;
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for (j = 0; j < SI_NUM_IMAGES; j++)
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memcpy(desc->list + j * 8, null_image_descriptor, 8 * 4);
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for (; j < SI_NUM_IMAGES + SI_NUM_SAMPLERS * 2; j++)
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memcpy(desc->list + j * 8, null_texture_descriptor, 8 * 4);
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}
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si_init_buffer_resources(&sctx->rw_buffers,
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@ -2061,7 +2045,7 @@ void si_init_all_descriptors(struct si_context *sctx)
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RADEON_PRIO_SHADER_RINGS, RADEON_PRIO_CONST_BUFFER,
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&ce_offset);
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si_init_descriptors(&sctx->vertex_buffers, SI_SGPR_VERTEX_BUFFERS,
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4, SI_NUM_VERTEX_BUFFERS, NULL, NULL);
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4, SI_NUM_VERTEX_BUFFERS, NULL);
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sctx->descriptors_dirty = u_bit_consecutive(0, SI_NUM_DESCS);
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@ -2800,9 +2800,7 @@ static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
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ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param,
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8 + GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS);
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ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param + 1,
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8 + GFX9_SGPR_TCS_SAMPLERS);
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ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param + 2,
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8 + GFX9_SGPR_TCS_IMAGES);
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8 + GFX9_SGPR_TCS_SAMPLERS_AND_IMAGES);
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unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR;
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ret = si_insert_input_ret_float(ctx, ret,
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@ -2827,9 +2825,7 @@ static void si_set_es_return_value_for_gs(struct si_shader_context *ctx)
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ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param,
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8 + GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS);
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ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param + 1,
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8 + GFX9_SGPR_GS_SAMPLERS);
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ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param + 2,
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8 + GFX9_SGPR_GS_IMAGES);
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8 + GFX9_SGPR_GS_SAMPLERS_AND_IMAGES);
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unsigned vgpr = 8 + GFX9_GS_NUM_USER_SGPR;
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for (unsigned i = 0; i < 5; i++) {
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@ -4061,13 +4057,12 @@ static void declare_per_stage_desc_pointers(struct si_shader_context *ctx,
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{
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params[(*num_params)++] = si_const_array(ctx->v4i32,
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SI_NUM_SHADER_BUFFERS + SI_NUM_CONST_BUFFERS);
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params[(*num_params)++] = si_const_array(ctx->v8i32, SI_NUM_SAMPLERS);
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params[(*num_params)++] = si_const_array(ctx->v8i32, SI_NUM_IMAGES);
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params[(*num_params)++] = si_const_array(ctx->v8i32,
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SI_NUM_IMAGES + SI_NUM_SAMPLERS * 2);
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if (assign_params) {
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ctx->param_const_and_shader_buffers = *num_params - 3;
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ctx->param_samplers = *num_params - 2;
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ctx->param_images = *num_params - 1;
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ctx->param_const_and_shader_buffers = *num_params - 2;
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ctx->param_samplers_and_images = *num_params - 1;
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}
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}
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@ -6666,7 +6661,6 @@ static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
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params[num_params++] = ctx->i64;
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params[num_params++] = ctx->i64;
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params[num_params++] = ctx->i64;
|
||||
params[num_params++] = ctx->i64;
|
||||
params[num_params++] = ctx->i32;
|
||||
params[num_params++] = ctx->i32;
|
||||
params[num_params++] = ctx->i32;
|
||||
|
|
@ -6680,7 +6674,6 @@ static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
|
|||
params[num_params++] = ctx->i64;
|
||||
params[num_params++] = ctx->i64;
|
||||
params[num_params++] = ctx->i64;
|
||||
params[num_params++] = ctx->i64;
|
||||
params[ctx->param_tcs_offchip_layout = num_params++] = ctx->i32;
|
||||
params[num_params++] = ctx->i32;
|
||||
params[num_params++] = ctx->i32;
|
||||
|
|
@ -7038,8 +7031,7 @@ static void si_build_ps_epilog_function(struct si_shader_context *ctx,
|
|||
/* Declare input SGPRs. */
|
||||
params[ctx->param_rw_buffers = num_params++] = ctx->i64;
|
||||
params[ctx->param_const_and_shader_buffers = num_params++] = ctx->i64;
|
||||
params[ctx->param_samplers = num_params++] = ctx->i64;
|
||||
params[ctx->param_images = num_params++] = ctx->i64;
|
||||
params[ctx->param_samplers_and_images = num_params++] = ctx->i64;
|
||||
assert(num_params == SI_PARAM_ALPHA_REF);
|
||||
params[SI_PARAM_ALPHA_REF] = ctx->f32;
|
||||
last_sgpr = SI_PARAM_ALPHA_REF;
|
||||
|
|
|
|||
|
|
@ -159,10 +159,8 @@ enum {
|
|||
SI_SGPR_RW_BUFFERS_HI,
|
||||
SI_SGPR_CONST_AND_SHADER_BUFFERS,
|
||||
SI_SGPR_CONST_AND_SHADER_BUFFERS_HI,
|
||||
SI_SGPR_SAMPLERS, /* images & sampler states interleaved */
|
||||
SI_SGPR_SAMPLERS_HI,
|
||||
SI_SGPR_IMAGES,
|
||||
SI_SGPR_IMAGES_HI,
|
||||
SI_SGPR_SAMPLERS_AND_IMAGES,
|
||||
SI_SGPR_SAMPLERS_AND_IMAGES_HI,
|
||||
SI_NUM_RESOURCE_SGPRS,
|
||||
|
||||
/* all VS variants */
|
||||
|
|
@ -197,19 +195,15 @@ enum {
|
|||
GFX9_SGPR_unused_to_align_the_next_pointer,
|
||||
GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS,
|
||||
GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS_HI,
|
||||
GFX9_SGPR_TCS_SAMPLERS, /* images & sampler states interleaved */
|
||||
GFX9_SGPR_TCS_SAMPLERS_HI,
|
||||
GFX9_SGPR_TCS_IMAGES,
|
||||
GFX9_SGPR_TCS_IMAGES_HI,
|
||||
GFX9_SGPR_TCS_SAMPLERS_AND_IMAGES,
|
||||
GFX9_SGPR_TCS_SAMPLERS_AND_IMAGES_HI,
|
||||
GFX9_TCS_NUM_USER_SGPR,
|
||||
|
||||
/* GFX9: Merged ES-GS (VS-GS or TES-GS). */
|
||||
GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS = SI_VS_NUM_USER_SGPR,
|
||||
GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS_HI,
|
||||
GFX9_SGPR_GS_SAMPLERS,
|
||||
GFX9_SGPR_GS_SAMPLERS_HI,
|
||||
GFX9_SGPR_GS_IMAGES,
|
||||
GFX9_SGPR_GS_IMAGES_HI,
|
||||
GFX9_SGPR_GS_SAMPLERS_AND_IMAGES,
|
||||
GFX9_SGPR_GS_SAMPLERS_AND_IMAGES_HI,
|
||||
GFX9_GS_NUM_USER_SGPR,
|
||||
|
||||
/* GS limits */
|
||||
|
|
@ -223,7 +217,7 @@ enum {
|
|||
|
||||
/* LLVM function parameter indices */
|
||||
enum {
|
||||
SI_NUM_RESOURCE_PARAMS = 4,
|
||||
SI_NUM_RESOURCE_PARAMS = 3,
|
||||
|
||||
/* PS only parameters */
|
||||
SI_PARAM_ALPHA_REF = SI_NUM_RESOURCE_PARAMS,
|
||||
|
|
|
|||
|
|
@ -110,8 +110,7 @@ struct si_shader_context {
|
|||
/* Parameter indices for LLVMGetParam. */
|
||||
int param_rw_buffers;
|
||||
int param_const_and_shader_buffers;
|
||||
int param_samplers;
|
||||
int param_images;
|
||||
int param_samplers_and_images;
|
||||
/* Common inputs for merged shaders. */
|
||||
int param_merged_wave_info;
|
||||
int param_merged_scratch_offset;
|
||||
|
|
|
|||
|
|
@ -180,7 +180,7 @@ image_fetch_rsrc(
|
|||
{
|
||||
struct si_shader_context *ctx = si_shader_context(bld_base);
|
||||
LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
|
||||
ctx->param_images);
|
||||
ctx->param_samplers_and_images);
|
||||
LLVMValueRef index;
|
||||
bool dcc_off = is_store;
|
||||
|
||||
|
|
@ -191,7 +191,8 @@ image_fetch_rsrc(
|
|||
unsigned images_writemask = info->images_store |
|
||||
info->images_atomic;
|
||||
|
||||
index = LLVMConstInt(ctx->i32, image->Register.Index, 0);
|
||||
index = LLVMConstInt(ctx->i32,
|
||||
si_get_image_slot(image->Register.Index), 0);
|
||||
|
||||
if (images_writemask & (1 << image->Register.Index))
|
||||
dcc_off = true;
|
||||
|
|
@ -208,6 +209,9 @@ image_fetch_rsrc(
|
|||
index = si_get_bounded_indirect_index(ctx, &image->Indirect,
|
||||
image->Register.Index,
|
||||
SI_NUM_IMAGES);
|
||||
index = LLVMBuildSub(ctx->gallivm.builder,
|
||||
LLVMConstInt(ctx->i32, SI_NUM_IMAGES - 1, 0),
|
||||
index, "");
|
||||
}
|
||||
|
||||
*rsrc = load_image_desc(ctx, rsrc_ptr, index, target);
|
||||
|
|
@ -1181,7 +1185,7 @@ static void tex_fetch_ptrs(
|
|||
LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
|
||||
{
|
||||
struct si_shader_context *ctx = si_shader_context(bld_base);
|
||||
LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers);
|
||||
LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
|
||||
const struct tgsi_full_instruction *inst = emit_data->inst;
|
||||
const struct tgsi_full_src_register *reg;
|
||||
unsigned target = inst->Texture.Texture;
|
||||
|
|
@ -1196,8 +1200,11 @@ static void tex_fetch_ptrs(
|
|||
®->Indirect,
|
||||
reg->Register.Index,
|
||||
SI_NUM_SAMPLERS);
|
||||
index = LLVMBuildAdd(ctx->gallivm.builder, index,
|
||||
LLVMConstInt(ctx->i32, SI_NUM_IMAGES / 2, 0), "");
|
||||
} else {
|
||||
index = LLVMConstInt(ctx->i32, reg->Register.Index, 0);
|
||||
index = LLVMConstInt(ctx->i32,
|
||||
si_get_sampler_slot(reg->Register.Index), 0);
|
||||
}
|
||||
|
||||
if (target == TGSI_TEXTURE_BUFFER)
|
||||
|
|
|
|||
|
|
@ -196,8 +196,7 @@ enum {
|
|||
*/
|
||||
enum {
|
||||
SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
|
||||
SI_SHADER_DESCS_SAMPLERS,
|
||||
SI_SHADER_DESCS_IMAGES,
|
||||
SI_SHADER_DESCS_SAMPLERS_AND_IMAGES,
|
||||
SI_NUM_SHADER_DESCS,
|
||||
};
|
||||
|
||||
|
|
@ -229,7 +228,7 @@ struct si_descriptors {
|
|||
unsigned ce_offset;
|
||||
|
||||
/* elements of the list that are changed and need to be uploaded */
|
||||
unsigned dirty_mask;
|
||||
uint64_t dirty_mask;
|
||||
|
||||
/* Whether CE is used to upload this descriptor array. */
|
||||
bool uses_ce;
|
||||
|
|
@ -387,4 +386,16 @@ static inline unsigned si_get_shaderbuf_slot(unsigned slot)
|
|||
return SI_NUM_SHADER_BUFFERS - 1 - slot;
|
||||
}
|
||||
|
||||
static inline unsigned si_get_sampler_slot(unsigned slot)
|
||||
{
|
||||
/* samplers are in slots [8..39], ascending */
|
||||
return SI_NUM_IMAGES / 2 + slot;
|
||||
}
|
||||
|
||||
static inline unsigned si_get_image_slot(unsigned slot)
|
||||
{
|
||||
/* images are in slots [15..0] (sampler slots [7..0]), descending */
|
||||
return SI_NUM_IMAGES - 1 - slot;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue