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nvc0/ir/emit: implement move to and logic ops on predicates

This commit is contained in:
Christoph Bumiller 2013-02-22 19:10:20 +01:00
parent ce7610f7d5
commit efe55075b5
1 changed files with 45 additions and 0 deletions
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45
src/gallium/drivers/nvc0/codegen/nv50_ir_emit_nvc0.cpp
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@ -676,6 +676,32 @@ CodeEmitterNVC0::emitNOT(Instruction *i)
void
CodeEmitterNVC0::emitLogicOp(const Instruction *i, uint8_t subOp)
{
if (i->def(0).getFile() == FILE_PREDICATE) {
code[0] = 0x00000004 | (subOp << 30);
code[1] = 0x0c000000;
emitPredicate(i);
defId(i->def(0), 17);
srcId(i->src(0), 20);
if (i->src(0).mod == Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 23;
srcId(i->src(1), 26);
if (i->src(1).mod == Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 29;
if (i->defExists(1)) {
defId(i->def(1), 14);
} else {
code[0] |= 7 << 14;
}
// (a OP b) OP c
if (i->predSrc != 2 && i->srcExists(2)) {
code[1] |= subOp << 21;
srcId(i->src(2), 17);
if (i->src(2).mod == Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 20;
} else {
code[1] |= 0x000e0000;
}
} else
if (i->encSize == 8) {
if (isLIMM(i->src(1), TYPE_U32)) {
emitForm_A(i, HEX64(38000000, 00000002));
@ -1525,6 +1551,25 @@ CodeEmitterNVC0::getSRegEncoding(const ValueRef& ref)
void
CodeEmitterNVC0::emitMOV(const Instruction *i)
{
if (i->def(0).getFile() == FILE_PREDICATE) {
if (i->src(0).getFile() == FILE_GPR) {
code[0] = 0xfc01c003;
code[1] = 0x1a8e0000;
srcId(i->src(0), 20);
} else {
code[0] = 0x0001c004;
code[1] = 0x0c0e0000;
if (i->src(0).getFile() == FILE_IMMEDIATE) {
code[0] |= 7 << 20;
if (!i->getSrc(0)->reg.data.u32)
code[0] |= 1 << 23;
} else {
srcId(i->src(0), 20);
}
}
defId(i->def(0), 17);
emitPredicate(i);
} else
if (i->src(0).getFile() == FILE_SYSTEM_VALUE) {
uint8_t sr = getSRegEncoding(i->src(0));