amd/addrlib: import Raven support
Cc: 17.1 <mesa-stable@lists.freedesktop.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
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@ -1193,6 +1193,20 @@ ChipFamily Gfx9Lib::HwlConvertChipFamily(
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m_settings.depthPipeXorDisable = 1;
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break;
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case FAMILY_RV:
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m_settings.isArcticIsland = 1;
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m_settings.isRaven = ASICREV_IS_RAVEN(uChipRevision);
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if (m_settings.isRaven)
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{
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m_settings.isDcn1 = 1;
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}
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m_settings.metaBaseAlignFix = 1;
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m_settings.depthPipeXorDisable = 1;
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break;
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default:
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ADDR_ASSERT(!"This should be a Fusion");
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break;
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@ -2734,6 +2748,35 @@ BOOL_32 Gfx9Lib::IsValidDisplaySwizzleMode(
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break;
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}
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}
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else if (m_settings.isDcn1)
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{
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switch (swizzleMode)
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{
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case ADDR_SW_4KB_D:
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case ADDR_SW_64KB_D:
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case ADDR_SW_VAR_D:
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case ADDR_SW_64KB_D_T:
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case ADDR_SW_4KB_D_X:
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case ADDR_SW_64KB_D_X:
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case ADDR_SW_VAR_D_X:
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support = (pIn->bpp == 64);
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break;
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case ADDR_SW_LINEAR:
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case ADDR_SW_4KB_S:
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case ADDR_SW_64KB_S:
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case ADDR_SW_VAR_S:
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case ADDR_SW_64KB_S_T:
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case ADDR_SW_4KB_S_X:
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case ADDR_SW_64KB_S_X:
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case ADDR_SW_VAR_S_X:
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support = (pIn->bpp <= 64);
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break;
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default:
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break;
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}
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}
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else
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{
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ADDR_NOT_IMPLEMENTED();
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@ -3195,6 +3238,20 @@ ADDR_E_RETURNCODE Gfx9Lib::HwlGetPreferredSurfaceSetting(
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// DCE12 does not support display surface to be _T swizzle mode
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prtXor = FALSE;
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}
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else if (m_settings.isDcn1)
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{
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// _R is not supported by Dcn1
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if (pIn->bpp == 64)
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{
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swType = ADDR_SW_D;
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}
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else
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{
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swType = ADDR_SW_S;
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}
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blockSet.micro = FALSE;
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}
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else
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{
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ADDR_NOT_IMPLEMENTED();
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@ -54,11 +54,13 @@ struct Gfx9ChipSettings
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// Asic/Generation name
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UINT_32 isArcticIsland : 1;
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UINT_32 isVega10 : 1;
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UINT_32 reserved0 : 30;
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UINT_32 isRaven : 1;
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UINT_32 reserved0 : 29;
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// Display engine IP version name
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UINT_32 isDce12 : 1;
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UINT_32 reserved1 : 31;
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UINT_32 isDcn1 : 1;
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UINT_32 reserved1 : 29;
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// Misc configuration bits
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UINT_32 metaBaseAlignFix : 1;
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@ -201,7 +203,7 @@ protected:
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if (IsXor(swizzleMode))
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{
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if (m_settings.isVega10)
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if (m_settings.isVega10 || m_settings.isRaven)
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{
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baseAlign = GetBlockSize(swizzleMode);
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}
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@ -49,6 +49,7 @@ enum {
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FAMILY_CZ,
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FAMILY_PI,
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FAMILY_AI,
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FAMILY_RV,
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FAMILY_LAST,
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};
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@ -185,4 +186,13 @@ enum {
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#define ASICREV_IS_VEGA10_P(eChipRev) \
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((eChipRev) >= AI_VEGA10_P_A0 && (eChipRev) < AI_UNKNOWN)
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/* RV specific rev IDs */
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enum {
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RAVEN_A0 = 0x01,
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RAVEN_UNKNOWN = 0xFF
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};
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#define ASICREV_IS_RAVEN(eChipRev) \
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((eChipRev) >= RAVEN_A0 && (eChipRev) < RAVEN_UNKNOWN)
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#endif /* AMDGPU_ID_H */
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