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radeon/llvm: Remove AMDIL MAD instruction defs

This commit is contained in:
Tom Stellard 2012-05-17 14:34:40 -04:00
parent d07473fcf4
commit ef8e66bc16
6 changed files with 14 additions and 7 deletions
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1
src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
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@ -34,7 +34,6 @@ use strict;
my @F32_MULTICLASSES = qw {
UnaryIntrinsicFloat
UnaryIntrinsicFloatScalar
TernaryIntrinsicFloat
};
my @I32_MULTICLASSES = qw {

3
src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
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@ -45,6 +45,9 @@ SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
default: return Op;
case AMDGPUIntrinsic::AMDIL_abs:
return LowerIntrinsicIABS(Op, DAG);
case AMDGPUIntrinsic::AMDIL_mad:
return DAG.getNode(AMDILISD::MAD, DL, VT, Op.getOperand(1),
Op.getOperand(2), Op.getOperand(3));
case AMDGPUIntrinsic::AMDIL_max:
return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),
Op.getOperand(2));

2
src/gallium/drivers/radeon/AMDILInstructions.td
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@ -251,7 +251,6 @@ defm POW : BinaryIntrinsicFloat<IL_OP_POW, int_AMDIL_pow>;
let hasIEEEFlag = 1 in {
let mayLoad = 0, mayStore=0 in {
defm MIN : BinaryIntrinsicFloat<IL_OP_MIN, int_AMDIL_min>;
defm MAD : TernaryIntrinsicFloat<IL_OP_MAD, int_AMDIL_mad>;
}
defm MOD : BinaryOpMCf32<IL_OP_MOD, frem>;
}
@ -270,7 +269,6 @@ defm LERP : TernaryIntrinsicFloat<IL_OP_LERP, int_AMDIL_lerp>;
}
defm SUB : BinaryOpMCf32<IL_OP_SUB, fsub>;
defm FABS : UnaryOpMCf32<IL_OP_ABS, fabs>;
defm FMAD : TernaryOpMCf32<IL_OP_MAD, IL_mad>;
defm NEAR : UnaryOpMCf32<IL_OP_ROUND_NEAR, fnearbyint>;
defm RND_Z : UnaryOpMCf32<IL_OP_ROUND_ZERO, ftrunc>;

6
src/gallium/drivers/radeon/R600Instructions.td
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@ -521,9 +521,9 @@ class MUL_LIT_Common <bits<32> inst> : R600_3OP <
class MULADD_Common <bits<32> inst> : R600_3OP <
inst, "MULADD",
[]> {
let AMDILOp = AMDILInst.MAD_f32;
}
[(set (f32 R600_Reg32:$dst),
(IL_mad R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2))]
>;
class CNDE_Common <bits<32> inst> : R600_3OP <
inst, "CNDE",

1
src/gallium/drivers/radeon/SIInstrInfo.cpp
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@ -106,7 +106,6 @@ MachineInstr * SIInstrInfo::convertToISA(MachineInstr & MI, MachineFunction &MF,
unsigned SIInstrInfo::getISAOpcode(unsigned AMDILopcode) const
{
switch (AMDILopcode) {
case AMDIL::MAD_f32: return AMDIL::V_MAD_LEGACY_F32;
//XXX We need a better way of detecting end of program
case AMDIL::RETURN: return AMDIL::S_ENDPGM;
default: return AMDGPUInstrInfo::getISAOpcode(AMDILopcode);

8
src/gallium/drivers/radeon/SIInstructions.td
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@ -964,4 +964,12 @@ def : Pat <
/* XXX: We are using IEEE MUL, not the 0 * anything = 0 MUL, is this correct? */
def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_F32_e32, VReg_32>;
/********** ================== **********/
/********** VOP3 Patterns **********/
/********** ================== **********/
def : Pat <(f32 (IL_mad AllReg_32:$src0, AllReg_32:$src1, AllReg_32:$src2)),
(V_MAD_LEGACY_F32 AllReg_32:$src0, AllReg_32:$src1, AllReg_32:$src2,
0, 0, 0, 0)>;
} // End isSI predicate