From ef675e685777ba87e62f374e1d74bbf0deb5734b Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Wed, 6 Oct 2021 14:45:35 -0700 Subject: [PATCH] anv: Program pixel hashing tables on XeHP. Note that this has an effect even for unfused native die platforms, since the pixel pipe hashing tables we intend to program aren't equivalent to the hardware's defaults on such configs. Reviewed-by: Caio Oliveira Part-of: --- src/intel/vulkan/genX_state.c | 38 +++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c index 8d7e08a8095..7d6fd065f7b 100644 --- a/src/intel/vulkan/genX_state.c +++ b/src/intel/vulkan/genX_state.c @@ -114,6 +114,44 @@ genX(emit_slice_hashing_state)(struct anv_device *device, p.SubsliceHashingTableEnable = true; p.SubsliceHashingTableEnableMask = true; } +#elif GFX_VERx10 == 125 + uint32_t ppipe_mask = 0; + for (unsigned p = 0; p < ARRAY_SIZE(device->info.ppipe_subslices); p++) { + if (device->info.ppipe_subslices[p]) + ppipe_mask |= (1u << p); + } + assert(ppipe_mask); + + if (!device->slice_hash.alloc_size) { + unsigned size = GENX(SLICE_HASH_TABLE_length) * 4; + device->slice_hash = + anv_state_pool_alloc(&device->dynamic_state_pool, size, 64); + + struct GENX(SLICE_HASH_TABLE) table; + + /* Note that the hardware expects an array with 7 tables, each + * table is intended to specify the pixel pipe hashing behavior + * for every possible slice count between 2 and 8, however that + * doesn't actually work, among other reasons due to hardware + * bugs that will cause the GPU to erroneously access the table + * at the wrong index in some cases, so in practice all 7 tables + * need to be initialized to the same value. + */ + for (unsigned i = 0; i < 7; i++) + intel_compute_pixel_hash_table_nway(16, 16, ppipe_mask, table.Entry[i][0]); + + GENX(SLICE_HASH_TABLE_pack)(NULL, device->slice_hash.map, &table); + } + + anv_batch_emit(batch, GENX(3DSTATE_SLICE_TABLE_STATE_POINTERS), ptr) { + ptr.SliceHashStatePointerValid = true; + ptr.SliceHashTableStatePointer = device->slice_hash.offset; + } + + anv_batch_emit(batch, GENX(3DSTATE_3D_MODE), mode) { + mode.SliceHashingTableEnable = true; + mode.SliceHashingTableEnableMask = true; + } #endif }