radv: Create internal cmdbuf when a graphics pipeline needs compute.
This is mainly going to be used by task shaders, because the HW implementation mismatches the API: - In the API, task shaders are considered graphics shaders which are part of a graphics pipeline and the draws are submitted to a graphics queue. - The HW requires the driver to dispatch task shaders on an async compute queue. When a pipeline is bound that has a task shader, create a driver-internal ACE (async compute engine) cmdbuf which we are going to submit to an ACE queue. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16531>
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@ -421,6 +421,8 @@ radv_destroy_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
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if (cmd_buffer->cs)
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cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
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if (cmd_buffer->ace_internal.cs)
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cmd_buffer->device->ws->cs_destroy(cmd_buffer->ace_internal.cs);
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for (unsigned i = 0; i < MAX_BIND_POINTS; i++) {
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struct radv_descriptor_set_header *set = &cmd_buffer->descriptors[i].push_set.set;
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@ -490,6 +492,8 @@ radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
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vk_command_buffer_reset(&cmd_buffer->vk);
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cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
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if (cmd_buffer->ace_internal.cs)
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cmd_buffer->device->ws->cs_reset(cmd_buffer->ace_internal.cs);
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list_for_each_entry_safe(struct radv_cmd_buffer_upload, up, &cmd_buffer->upload.list, list)
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{
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@ -686,6 +690,30 @@ radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
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radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
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}
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static struct radeon_cmdbuf *
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radv_ace_internal_create(struct radv_cmd_buffer *cmd_buffer)
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{
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assert(!cmd_buffer->ace_internal.cs);
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struct radv_device *device = cmd_buffer->device;
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struct radeon_cmdbuf *ace_cs = device->ws->cs_create(device->ws, AMD_IP_COMPUTE);
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if (!ace_cs) {
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cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
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}
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return ace_cs;
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}
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static VkResult
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radv_ace_internal_finalize(struct radv_cmd_buffer *cmd_buffer)
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{
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assert(cmd_buffer->ace_internal.cs);
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struct radv_device *device = cmd_buffer->device;
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struct radeon_cmdbuf *ace_cs = cmd_buffer->ace_internal.cs;
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return device->ws->cs_finalize(ace_cs);
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}
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static void
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radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer, enum radv_cmd_flush_bits flags)
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{
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@ -5247,6 +5275,13 @@ radv_EndCommandBuffer(VkCommandBuffer commandBuffer)
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if (cmd_buffer->gds_needed)
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cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
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/* Finalize the internal compute command stream, if it exists. */
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if (cmd_buffer->ace_internal.cs) {
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VkResult result = radv_ace_internal_finalize(cmd_buffer);
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if (result != VK_SUCCESS)
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return vk_error(cmd_buffer, result);
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}
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si_emit_cache_flush(cmd_buffer);
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}
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@ -5402,6 +5437,12 @@ radv_CmdBindPipeline(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipeline
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pipeline->shaders[MESA_SHADER_MESH]->info.ms.needs_ms_scratch_ring;
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if (radv_pipeline_has_stage(graphics_pipeline, MESA_SHADER_TASK)) {
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if (!cmd_buffer->ace_internal.cs) {
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cmd_buffer->ace_internal.cs = radv_ace_internal_create(cmd_buffer);
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if (!cmd_buffer->ace_internal.cs)
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return;
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}
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cmd_buffer->task_rings_needed = true;
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}
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break;
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@ -1638,6 +1638,14 @@ struct radv_cmd_buffer {
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uint64_t mec_inv_pred_va; /* For inverted predication when using MEC. */
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bool mec_inv_pred_emitted; /* To ensure we don't have to repeat inverting the VA. */
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struct {
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/**
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* Internal command stream that is used when some graphics work
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* also requires a submission to the compute queue.
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*/
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struct radeon_cmdbuf *cs;
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} ace_internal;
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/**
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* Whether a query pool has been resetted and we have to flush caches.
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*/
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