From eedc0b59b710c9e7c284e3ceaae5a43e2f19bcb0 Mon Sep 17 00:00:00 2001
From: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Date: Thu, 29 Jul 2021 09:09:57 +0200
Subject: [PATCH] ac/surface: copy the CMASK equation to radeon_surf
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Only GFX9 is currently supported.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12140>
---
 src/amd/common/ac_surface.c | 24 ++++++++++++++++++++++++
 src/amd/common/ac_surface.h |  3 +++
 2 files changed, 27 insertions(+)

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index ff7bb44a4ab..31b1f7f8d32 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -1491,6 +1491,28 @@ static void ac_copy_dcc_equation(const struct radeon_info *info,
    }
 }
 
+static void ac_copy_cmask_equation(const struct radeon_info *info,
+                                   ADDR2_COMPUTE_CMASK_INFO_OUTPUT *cmask,
+                                   struct gfx9_meta_equation *equation)
+{
+   equation->meta_block_width = cmask->metaBlkWidth;
+   equation->meta_block_height = cmask->metaBlkHeight;
+   equation->meta_block_depth = 1;
+
+   if (info->chip_class == GFX9) {
+      assert(cmask->equation.gfx9.num_bits <= ARRAY_SIZE(equation->u.gfx9.bit));
+
+      equation->u.gfx9.num_bits = cmask->equation.gfx9.num_bits;
+      equation->u.gfx9.num_pipe_bits = cmask->equation.gfx9.numPipeBits;
+      for (unsigned b = 0; b < ARRAY_SIZE(equation->u.gfx9.bit); b++) {
+         for (unsigned c = 0; c < ARRAY_SIZE(equation->u.gfx9.bit[b].coord); c++) {
+            equation->u.gfx9.bit[b].coord[c].dim = cmask->equation.gfx9.bit[b].coord[c].dim;
+            equation->u.gfx9.bit[b].coord[c].ord = cmask->equation.gfx9.bit[b].coord[c].ord;
+         }
+      }
+   }
+}
+
 static void ac_copy_htile_equation(const struct radeon_info *info,
                                    ADDR2_COMPUTE_HTILE_INFO_OUTPUT *htile,
                                    struct gfx9_meta_equation *equation)
@@ -1907,6 +1929,8 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_
          surf->cmask_height = cout.height;
          surf->u.gfx9.color.cmask_level0.offset = meta_mip_info[0].offset;
          surf->u.gfx9.color.cmask_level0.size = meta_mip_info[0].sliceSize;
+
+         ac_copy_cmask_equation(info, &cout, &surf->u.gfx9.color.cmask_equation);
       }
    }
 
diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 4f328132ff9..41a6273f936 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -287,6 +287,9 @@ struct gfx9_surf_layout {
          /* For DCC retiling. */
          struct gfx9_meta_equation dcc_equation; /* 2D only */
          struct gfx9_meta_equation display_dcc_equation;
+
+         /* For FCE compute. */
+         struct gfx9_meta_equation cmask_equation; /* 2D only */
       } color;
 
       /* Z/S */