vc4: Make scheduling of NOPs a separate step from QIR -> QPU translation.
This should also be used as a way to pair QIR instructions into QPU instructions later.
This commit is contained in:
Eric Anholt
parent
c293927511
commit
eea1d36915
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@ -600,7 +600,7 @@ vc4_shader_tgsi_to_qir(struct vc4_compiled_shader *shader, enum qstage stage,
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if (vc4_debug & VC4_DEBUG_SHADERDB) {
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fprintf(stderr, "SHADER-DB: %s: %d instructions\n",
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qir_get_stage_name(c->stage), c->num_qpu_insts);
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qir_get_stage_name(c->stage), c->qpu_inst_count);
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fprintf(stderr, "SHADER-DB: %s: %d uniforms\n",
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qir_get_stage_name(c->stage), trans->num_uniforms);
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}
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@ -647,7 +647,7 @@ vc4_fs_compile(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
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shader->num_inputs = trans->num_inputs;
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copy_uniform_state_to_shader(shader, 0, trans);
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shader->bo = vc4_bo_alloc_mem(vc4->screen, trans->c->qpu_insts,
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trans->c->num_qpu_insts * sizeof(uint64_t),
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trans->c->qpu_inst_count * sizeof(uint64_t),
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"fs_code");
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qir_compile_destroy(trans->c);
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@ -668,8 +668,8 @@ vc4_vs_compile(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
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&key->base);
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copy_uniform_state_to_shader(shader, 1, cs_trans);
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uint32_t vs_size = vs_trans->c->num_qpu_insts * sizeof(uint64_t);
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uint32_t cs_size = cs_trans->c->num_qpu_insts * sizeof(uint64_t);
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uint32_t vs_size = vs_trans->c->qpu_inst_count * sizeof(uint64_t);
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uint32_t cs_size = cs_trans->c->qpu_inst_count * sizeof(uint64_t);
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shader->coord_shader_offset = vs_size; /* XXX: alignment? */
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shader->bo = vc4_bo_alloc(vc4->screen,
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shader->coord_shader_offset + cs_size,
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@ -126,8 +126,10 @@ struct qcompile {
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struct simple_node instructions;
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uint32_t immediates[1024];
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struct simple_node qpu_inst_list;
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uint64_t *qpu_insts;
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uint32_t num_qpu_insts;
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uint32_t qpu_inst_count;
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uint32_t qpu_inst_size;
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};
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struct qcompile *qir_compile_init(void);
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@ -33,13 +33,34 @@ vc4_dump_program(struct qcompile *c)
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{
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fprintf(stderr, "%s:\n", qir_get_stage_name(c->stage));
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for (int i = 0; i < c->num_qpu_insts; i++) {
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for (int i = 0; i < c->qpu_inst_count; i++) {
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fprintf(stderr, "0x%016"PRIx64" ", c->qpu_insts[i]);
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vc4_qpu_disasm(&c->qpu_insts[i], 1);
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fprintf(stderr, "\n");
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}
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}
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struct queued_qpu_inst {
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struct simple_node link;
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uint64_t inst;
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};
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static void
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queue(struct qcompile *c, uint64_t inst)
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{
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struct queued_qpu_inst *q = calloc(1, sizeof(*q));
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q->inst = inst;
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insert_at_tail(&c->qpu_inst_list, &q->link);
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}
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static uint64_t *
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last_inst(struct qcompile *c)
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{
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struct queued_qpu_inst *q =
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(struct queued_qpu_inst *)last_elem(&c->qpu_inst_list);
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return &q->inst;
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}
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/**
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* This is used to resolve the fact that we might register-allocate two
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* different operands of an instruction to the same physical register file
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@ -50,23 +71,119 @@ vc4_dump_program(struct qcompile *c)
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* instruction, instead.
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*/
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static void
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fixup_raddr_conflict(uint64_t *insts, uint32_t *ni,
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fixup_raddr_conflict(struct qcompile *c,
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struct qpu_reg src0, struct qpu_reg *src1)
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{
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if ((src0.mux == QPU_MUX_A || src0.mux == QPU_MUX_B) &&
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(src1->mux == QPU_MUX_A || src1->mux == QPU_MUX_B) &&
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src0.addr != src1->addr) {
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insts[(*ni)++] = qpu_inst(qpu_a_MOV(qpu_r3(), *src1),
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qpu_m_NOP());
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queue(c, qpu_inst(qpu_a_MOV(qpu_r3(), *src1),
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qpu_m_NOP()));
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*src1 = qpu_r3();
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}
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}
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static void
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serialize_one_inst(struct qcompile *c, uint64_t inst)
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{
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if (c->qpu_inst_count >= c->qpu_inst_size) {
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c->qpu_inst_size = MAX2(16, c->qpu_inst_size * 2);
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c->qpu_insts = realloc(c->qpu_insts,
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c->qpu_inst_size * sizeof(uint64_t));
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}
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c->qpu_insts[c->qpu_inst_count++] = inst;
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}
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static void
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serialize_insts(struct qcompile *c)
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{
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int last_sfu_write = -10;
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while (!is_empty_list(&c->qpu_inst_list)) {
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struct queued_qpu_inst *q =
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(struct queued_qpu_inst *)first_elem(&c->qpu_inst_list);
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uint32_t last_waddr_a = QPU_W_NOP, last_waddr_b = QPU_W_NOP;
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uint32_t raddr_a = QPU_GET_FIELD(q->inst, QPU_RADDR_A);
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uint32_t raddr_b = QPU_GET_FIELD(q->inst, QPU_RADDR_B);
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if (c->qpu_inst_count > 0) {
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uint64_t last_inst = c->qpu_insts[c->qpu_inst_count -
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1];
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uint32_t last_waddr_add = QPU_GET_FIELD(last_inst,
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QPU_WADDR_ADD);
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uint32_t last_waddr_mul = QPU_GET_FIELD(last_inst,
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QPU_WADDR_MUL);
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if (last_inst & QPU_WS) {
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last_waddr_a = last_waddr_mul;
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last_waddr_b = last_waddr_add;
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} else {
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last_waddr_a = last_waddr_add;
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last_waddr_b = last_waddr_mul;
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}
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}
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uint32_t src_muxes[] = {
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QPU_GET_FIELD(q->inst, QPU_ADD_A),
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QPU_GET_FIELD(q->inst, QPU_ADD_B),
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QPU_GET_FIELD(q->inst, QPU_MUL_A),
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QPU_GET_FIELD(q->inst, QPU_MUL_B),
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};
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/* "An instruction must not read from a location in physical
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* regfile A or B that was written to by the previous
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* instruction."
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*/
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bool needs_raddr_vs_waddr_nop = false;
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bool reads_r4 = false;
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for (int i = 0; i < ARRAY_SIZE(src_muxes); i++) {
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if ((raddr_a < 32 &&
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src_muxes[i] == QPU_MUX_A &&
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last_waddr_a == raddr_a) ||
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(raddr_b < 32 &&
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src_muxes[i] == QPU_MUX_B &&
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last_waddr_b == raddr_b)) {
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needs_raddr_vs_waddr_nop = true;
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}
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if (src_muxes[i] == QPU_MUX_R4)
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reads_r4 = true;
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}
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if (needs_raddr_vs_waddr_nop) {
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serialize_one_inst(c, qpu_inst(qpu_a_NOP(),
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qpu_m_NOP()));
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}
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/* "After an SFU lookup instruction, accumulator r4 must not
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* be read in the following two instructions. Any other
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* instruction that results in r4 being written (that is, TMU
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* read, TLB read, SFU lookup) cannot occur in the two
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* instructions following an SFU lookup."
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*/
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if (reads_r4) {
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while (c->qpu_inst_count - last_sfu_write < 3) {
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serialize_one_inst(c, qpu_inst(qpu_a_NOP(),
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qpu_m_NOP()));
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}
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}
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uint32_t waddr_a = QPU_GET_FIELD(q->inst, QPU_WADDR_ADD);
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uint32_t waddr_m = QPU_GET_FIELD(q->inst, QPU_WADDR_MUL);
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if ((waddr_a >= QPU_W_SFU_RECIP && waddr_a <= QPU_W_SFU_LOG) ||
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(waddr_m >= QPU_W_SFU_RECIP && waddr_m <= QPU_W_SFU_LOG)) {
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last_sfu_write = c->qpu_inst_count;
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}
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serialize_one_inst(c, q->inst);
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remove_from_list(&q->link);
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free(q);
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}
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}
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void
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vc4_generate_code(struct qcompile *c)
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{
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uint64_t *insts = malloc(sizeof(uint64_t) * 1024); /* XXX: sizing */
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uint32_t ni = 0;
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struct qpu_reg allocate_to_qpu_reg[3 + 32 + 32];
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bool reg_in_use[ARRAY_SIZE(allocate_to_qpu_reg)];
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int *reg_allocated = calloc(c->num_temps, sizeof(*reg_allocated));
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@ -84,6 +201,8 @@ vc4_generate_code(struct qcompile *c)
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for (int i = 0; i < 32; i++)
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allocate_to_qpu_reg[i + 3 + 32] = qpu_rb(i);
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make_empty_list(&c->qpu_inst_list);
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struct simple_node *node;
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foreach(node, &c->instructions) {
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struct qinst *qinst = (struct qinst *)node;
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@ -99,8 +218,8 @@ vc4_generate_code(struct qcompile *c)
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switch (c->stage) {
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case QSTAGE_VERT:
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case QSTAGE_COORD:
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insts[ni++] = qpu_load_imm_ui(qpu_vrsetup(), 0x00401a00);
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insts[ni++] = qpu_load_imm_ui(qpu_vwsetup(), 0x00001a00);
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queue(c, qpu_load_imm_ui(qpu_vrsetup(), 0x00401a00));
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queue(c, qpu_load_imm_ui(qpu_vwsetup(), 0x00001a00));
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break;
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case QSTAGE_FRAG:
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break;
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@ -208,8 +327,8 @@ vc4_generate_code(struct qcompile *c)
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/* Skip emitting the MOV if it's a no-op. */
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if (dst.mux == QPU_MUX_A || dst.mux == QPU_MUX_B ||
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dst.mux != src[0].mux || dst.addr != src[0].addr) {
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insts[ni++] = qpu_inst(qpu_a_MOV(dst, src[0]),
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qpu_m_NOP());
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queue(c, qpu_inst(qpu_a_MOV(dst, src[0]),
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qpu_m_NOP()));
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}
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break;
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@ -217,30 +336,28 @@ vc4_generate_code(struct qcompile *c)
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case QOP_SNE:
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case QOP_SGE:
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case QOP_SLT:
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fixup_raddr_conflict(insts, &ni, src[0], &src[1]);
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insts[ni++] = qpu_inst(qpu_a_SUB(qpu_ra(QPU_W_NOP),
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src[0], src[1]),
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qpu_m_NOP());
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insts[ni - 1] |= QPU_SF;
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fixup_raddr_conflict(c, src[0], &src[1]);
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queue(c, qpu_inst(qpu_a_SUB(qpu_ra(QPU_W_NOP),
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src[0], src[1]),
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qpu_m_NOP()));
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*last_inst(c) |= QPU_SF;
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insts[ni++] = qpu_load_imm_f(dst, 0.0);
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insts[ni++] = qpu_load_imm_f(dst, 1.0);
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insts[ni - 1] = ((insts[ni - 1] & ~QPU_COND_ADD_MASK)
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queue(c, qpu_load_imm_f(dst, 0.0));
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queue(c, qpu_load_imm_f(dst, 1.0));
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*last_inst(c) = ((*last_inst(c) & ~QPU_COND_ADD_MASK)
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| QPU_SET_FIELD(compareflags[qinst->op - QOP_SEQ],
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QPU_COND_ADD));
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break;
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case QOP_VPM_WRITE:
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insts[ni++] = qpu_inst(qpu_a_MOV(qpu_ra(QPU_W_VPM),
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src[0]),
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qpu_m_NOP());
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queue(c, qpu_inst(qpu_a_MOV(qpu_ra(QPU_W_VPM), src[0]),
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qpu_m_NOP()));
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break;
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case QOP_VPM_READ:
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insts[ni++] = qpu_inst(qpu_a_MOV(dst,
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qpu_ra(QPU_R_VPM)),
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qpu_m_NOP());
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queue(c, qpu_inst(qpu_a_MOV(dst, qpu_ra(QPU_R_VPM)),
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qpu_m_NOP()));
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break;
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case QOP_RCP:
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@ -249,70 +366,70 @@ vc4_generate_code(struct qcompile *c)
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case QOP_LOG2:
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switch (qinst->op) {
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case QOP_RCP:
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insts[ni++] = qpu_inst(qpu_a_MOV(qpu_rb(QPU_W_SFU_RECIP),
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src[0]),
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qpu_m_NOP());
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queue(c, qpu_inst(qpu_a_MOV(qpu_rb(QPU_W_SFU_RECIP),
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src[0]),
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qpu_m_NOP()));
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break;
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case QOP_RSQ:
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insts[ni++] = qpu_inst(qpu_a_MOV(qpu_rb(QPU_W_SFU_RECIPSQRT),
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src[0]),
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qpu_m_NOP());
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queue(c, qpu_inst(qpu_a_MOV(qpu_rb(QPU_W_SFU_RECIPSQRT),
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src[0]),
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qpu_m_NOP()));
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break;
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case QOP_EXP2:
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insts[ni++] = qpu_inst(qpu_a_MOV(qpu_rb(QPU_W_SFU_EXP),
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src[0]),
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qpu_m_NOP());
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queue(c, qpu_inst(qpu_a_MOV(qpu_rb(QPU_W_SFU_EXP),
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src[0]),
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qpu_m_NOP()));
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break;
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case QOP_LOG2:
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insts[ni++] = qpu_inst(qpu_a_MOV(qpu_rb(QPU_W_SFU_LOG),
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src[0]),
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qpu_m_NOP());
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queue(c, qpu_inst(qpu_a_MOV(qpu_rb(QPU_W_SFU_LOG),
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src[0]),
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qpu_m_NOP()));
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break;
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default:
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abort();
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}
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insts[ni++] = qpu_inst(qpu_a_NOP(), qpu_m_NOP());
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insts[ni++] = qpu_inst(qpu_a_NOP(), qpu_m_NOP());
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insts[ni++] = qpu_inst(qpu_a_MOV(dst, qpu_r4()),
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qpu_m_NOP());
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queue(c, qpu_inst(qpu_a_MOV(dst, qpu_r4()),
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qpu_m_NOP()));
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break;
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case QOP_PACK_COLORS:
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for (int i = 0; i < 4; i++) {
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insts[ni++] = qpu_inst(qpu_a_NOP(),
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qpu_m_MOV(qpu_r3(), src[i]));
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insts[ni - 1] |= QPU_PM;
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insts[ni - 1] |= QPU_SET_FIELD(QPU_PACK_MUL_8A + i,
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queue(c, qpu_inst(qpu_a_NOP(),
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qpu_m_MOV(qpu_r3(), src[i])));
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*last_inst(c) |= QPU_PM;
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*last_inst(c) |= QPU_SET_FIELD(QPU_PACK_MUL_8A + i,
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QPU_PACK);
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}
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insts[ni++] = qpu_inst(qpu_a_MOV(dst, qpu_r3()),
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qpu_m_NOP());
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queue(c, qpu_inst(qpu_a_MOV(dst, qpu_r3()),
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qpu_m_NOP()));
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break;
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case QOP_TLB_COLOR_WRITE:
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insts[ni++] = qpu_inst(qpu_a_MOV(qpu_tlbc(),
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src[0]),
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qpu_m_NOP());
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queue(c, qpu_inst(qpu_a_MOV(qpu_tlbc(),
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src[0]),
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qpu_m_NOP()));
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break;
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case QOP_VARY_ADD_C:
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insts[ni++] = qpu_inst(qpu_a_FADD(dst,
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src[0], qpu_r5()),
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qpu_m_NOP());
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queue(c, qpu_inst(qpu_a_FADD(dst,
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src[0], qpu_r5()),
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qpu_m_NOP()));
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break;
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case QOP_PACK_SCALED:
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insts[ni++] = qpu_inst(qpu_a_MOV(dst, src[0]),
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qpu_m_NOP());
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insts[ni - 1] |= QPU_SET_FIELD(QPU_PACK_A_16A, QPU_PACK);
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queue(c, qpu_inst(qpu_a_MOV(dst, src[0]),
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qpu_m_NOP()));
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*last_inst(c) |= QPU_SET_FIELD(QPU_PACK_A_16A,
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QPU_PACK);
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insts[ni++] = qpu_inst(qpu_a_MOV(dst, src[1]),
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qpu_m_NOP());
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insts[ni - 1] |= QPU_SET_FIELD(QPU_PACK_A_16B, QPU_PACK);
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queue(c, qpu_inst(qpu_a_MOV(dst, src[1]),
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qpu_m_NOP()));
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*last_inst(c) |= QPU_SET_FIELD(QPU_PACK_A_16B,
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QPU_PACK);
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break;
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@ -327,51 +444,54 @@ vc4_generate_code(struct qcompile *c)
|
|||
if (qir_get_op_nsrc(qinst->op) == 1)
|
||||
src[1] = src[0];
|
||||
|
||||
fixup_raddr_conflict(insts, &ni, src[0], &src[1]);
|
||||
fixup_raddr_conflict(c, src[0], &src[1]);
|
||||
|
||||
if (translate[qinst->op].is_mul) {
|
||||
insts[ni++] = qpu_inst(qpu_a_NOP(),
|
||||
qpu_m_alu2(translate[qinst->op].op,
|
||||
dst, src[0], src[1]));
|
||||
queue(c, qpu_inst(qpu_a_NOP(),
|
||||
qpu_m_alu2(translate[qinst->op].op,
|
||||
dst,
|
||||
src[0], src[1])));
|
||||
} else {
|
||||
insts[ni++] = qpu_inst(qpu_a_alu2(translate[qinst->op].op,
|
||||
dst, src[0], src[1]),
|
||||
qpu_m_NOP());
|
||||
queue(c, qpu_inst(qpu_a_alu2(translate[qinst->op].op,
|
||||
dst,
|
||||
src[0], src[1]),
|
||||
qpu_m_NOP()));
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
if ((dst.mux == QPU_MUX_A || dst.mux == QPU_MUX_B) &&
|
||||
dst.addr < 32)
|
||||
insts[ni++] = qpu_inst(qpu_a_NOP(), qpu_m_NOP());
|
||||
}
|
||||
|
||||
/* thread end can't have VPM write */
|
||||
if (QPU_GET_FIELD(insts[ni - 1], QPU_WADDR_ADD) == QPU_W_VPM ||
|
||||
QPU_GET_FIELD(insts[ni - 1], QPU_WADDR_MUL) == QPU_W_VPM)
|
||||
insts[ni++] = qpu_inst(qpu_a_NOP(), qpu_m_NOP());
|
||||
serialize_insts(c);
|
||||
|
||||
insts[ni - 1] = qpu_set_sig(insts[ni - 1], QPU_SIG_PROG_END);
|
||||
insts[ni++] = qpu_inst(qpu_a_NOP(), qpu_m_NOP());
|
||||
insts[ni++] = qpu_inst(qpu_a_NOP(), qpu_m_NOP());
|
||||
/* thread end can't have VPM write */
|
||||
if (QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
|
||||
QPU_WADDR_ADD) == QPU_W_VPM ||
|
||||
QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
|
||||
QPU_WADDR_MUL) == QPU_W_VPM) {
|
||||
serialize_one_inst(c, qpu_inst(qpu_a_NOP(), qpu_m_NOP()));
|
||||
}
|
||||
|
||||
c->qpu_insts[c->qpu_inst_count - 1] =
|
||||
qpu_set_sig(c->qpu_insts[c->qpu_inst_count - 1],
|
||||
QPU_SIG_PROG_END);
|
||||
serialize_one_inst(c, qpu_inst(qpu_a_NOP(), qpu_m_NOP()));
|
||||
serialize_one_inst(c, qpu_inst(qpu_a_NOP(), qpu_m_NOP()));
|
||||
|
||||
switch (c->stage) {
|
||||
case QSTAGE_VERT:
|
||||
case QSTAGE_COORD:
|
||||
break;
|
||||
case QSTAGE_FRAG:
|
||||
insts[2] = qpu_set_sig(insts[2], QPU_SIG_WAIT_FOR_SCOREBOARD);
|
||||
insts[ni - 1] = qpu_set_sig(insts[ni - 1],
|
||||
QPU_SIG_SCOREBOARD_UNLOCK);
|
||||
c->qpu_insts[2] = qpu_set_sig(c->qpu_insts[2],
|
||||
QPU_SIG_WAIT_FOR_SCOREBOARD);
|
||||
c->qpu_insts[c->qpu_inst_count - 1] =
|
||||
qpu_set_sig(c->qpu_insts[c->qpu_inst_count - 1],
|
||||
QPU_SIG_SCOREBOARD_UNLOCK);
|
||||
break;
|
||||
}
|
||||
|
||||
c->qpu_insts = insts;
|
||||
c->num_qpu_insts = ni;
|
||||
|
||||
if (vc4_debug & VC4_DEBUG_QPU)
|
||||
vc4_dump_program(c);
|
||||
|
||||
vc4_qpu_validate(insts, ni);
|
||||
vc4_qpu_validate(c->qpu_insts, c->qpu_inst_count);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue