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i965/fs: Implement ARB_shader_group_vote operations 

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Matt Turner 2017-06-20 22:39:22 -07:00
parent 93dc736f4e
commit ee9fa4ac18
1 changed files with 50 additions and 0 deletions
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50
src/intel/compiler/brw_fs_nir.cpp
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@ -4118,6 +4118,56 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
break;
}
case nir_intrinsic_vote_any: {
const fs_builder ubld = bld.exec_all();
/* The any/all predicates do not consider channel enables. To prevent
* dead channels from affecting the result, we initialize the flag with
* with the identity value for the logical operation.
*/
ubld.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
bld.CMP(bld.null_reg_d(), get_nir_src(instr->src[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ);
bld.MOV(dest, brw_imm_d(-1));
set_predicate(dispatch_width == 8 ?
BRW_PREDICATE_ALIGN1_ANY8H :
BRW_PREDICATE_ALIGN1_ANY16H,
bld.SEL(dest, dest, brw_imm_d(0)));
break;
}
case nir_intrinsic_vote_all: {
const fs_builder ubld = bld.exec_all();
/* The any/all predicates do not consider channel enables. To prevent
* dead channels from affecting the result, we initialize the flag with
* with the identity value for the logical operation.
*/
ubld.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
bld.CMP(bld.null_reg_d(), get_nir_src(instr->src[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ);
bld.MOV(dest, brw_imm_d(-1));
set_predicate(dispatch_width == 8 ?
BRW_PREDICATE_ALIGN1_ALL8H :
BRW_PREDICATE_ALIGN1_ALL16H,
bld.SEL(dest, dest, brw_imm_d(0)));
break;
}
case nir_intrinsic_vote_eq: {
fs_reg value = get_nir_src(instr->src[0]);
fs_reg uniformized = bld.emit_uniformize(value);
const fs_builder ubld = bld.exec_all();
/* The any/all predicates do not consider channel enables. To prevent
* dead channels from affecting the result, we initialize the flag with
* with the identity value for the logical operation.
*/
ubld.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
bld.CMP(bld.null_reg_d(), value, uniformized, BRW_CONDITIONAL_Z);
bld.MOV(dest, brw_imm_d(-1));
set_predicate(dispatch_width == 8 ?
BRW_PREDICATE_ALIGN1_ALL8H :
BRW_PREDICATE_ALIGN1_ALL16H,
bld.SEL(dest, dest, brw_imm_d(0)));
break;
}
default:
unreachable("unknown intrinsic");
}