gallium: assorted additions and fixes to Cell SPE rtasm code
Fix incorrect opcode for fsmbi. Added "macro" functions for loading floats/ints, register complement, zero, move. Added #defines for return address and stack pointer registers. Added assertions to check that the instruction buffer doesn't overflow.
This commit is contained in:
Brian Paul
parent
04ae4fba3c
commit
ee582fd3a7
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@ -151,8 +151,8 @@ static void emit_RR(struct spe_function *p, unsigned op, unsigned rT,
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inst.inst.rB = rB;
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inst.inst.rA = rA;
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inst.inst.rT = rT;
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*p->csr = inst.bits;
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p->csr++;
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p->store[p->num_inst++] = inst.bits;
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assert(p->num_inst <= p->max_inst);
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}
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@ -165,8 +165,8 @@ static void emit_RRR(struct spe_function *p, unsigned op, unsigned rT,
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inst.inst.rB = rB;
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inst.inst.rA = rA;
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inst.inst.rC = rC;
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*p->csr = inst.bits;
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p->csr++;
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p->store[p->num_inst++] = inst.bits;
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assert(p->num_inst <= p->max_inst);
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}
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@ -178,8 +178,8 @@ static void emit_RI7(struct spe_function *p, unsigned op, unsigned rT,
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inst.inst.i7 = imm;
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inst.inst.rA = rA;
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inst.inst.rT = rT;
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*p->csr = inst.bits;
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p->csr++;
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p->store[p->num_inst++] = inst.bits;
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assert(p->num_inst <= p->max_inst);
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}
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@ -192,8 +192,8 @@ static void emit_RI8(struct spe_function *p, unsigned op, unsigned rT,
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inst.inst.i8 = imm;
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inst.inst.rA = rA;
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inst.inst.rT = rT;
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*p->csr = inst.bits;
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p->csr++;
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p->store[p->num_inst++] = inst.bits;
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assert(p->num_inst <= p->max_inst);
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}
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@ -206,8 +206,8 @@ static void emit_RI10(struct spe_function *p, unsigned op, unsigned rT,
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inst.inst.i10 = imm;
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inst.inst.rA = rA;
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inst.inst.rT = rT;
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*p->csr = inst.bits;
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p->csr++;
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p->store[p->num_inst++] = inst.bits;
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assert(p->num_inst <= p->max_inst);
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}
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@ -218,8 +218,8 @@ static void emit_RI16(struct spe_function *p, unsigned op, unsigned rT,
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inst.inst.op = op;
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inst.inst.i16 = imm;
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inst.inst.rT = rT;
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*p->csr = inst.bits;
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p->csr++;
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p->store[p->num_inst++] = inst.bits;
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assert(p->num_inst <= p->max_inst);
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}
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@ -230,8 +230,8 @@ static void emit_RI18(struct spe_function *p, unsigned op, unsigned rT,
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inst.inst.op = op;
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inst.inst.i18 = imm;
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inst.inst.rT = rT;
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*p->csr = inst.bits;
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p->csr++;
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p->store[p->num_inst++] = inst.bits;
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assert(p->num_inst <= p->max_inst);
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}
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@ -307,8 +307,9 @@ void _name (struct spe_function *p, int imm) \
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void spe_init_func(struct spe_function *p, unsigned code_size)
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{
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p->store = align_malloc(code_size, 16);
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p->csr = p->store;
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p->num_inst = 0;
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p->max_inst = code_size / SPE_INST_SIZE;
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/* Conservatively treat R0 - R2 and R80 - R127 as non-volatile.
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*/
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p->regs[0] = ~7;
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@ -318,11 +319,11 @@ void spe_init_func(struct spe_function *p, unsigned code_size)
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void spe_release_func(struct spe_function *p)
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{
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assert(p->num_inst <= p->max_inst);
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if (p->store != NULL) {
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align_free(p->store);
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}
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p->store = NULL;
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p->csr = NULL;
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}
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@ -337,6 +338,7 @@ int spe_allocate_available_register(struct spe_function *p)
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const uint64_t mask = (1ULL << (i % 64));
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const unsigned idx = i / 64;
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assert(idx < 2);
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if ((p->regs[idx] & mask) != 0) {
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p->regs[idx] &= ~mask;
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return i;
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@ -371,6 +373,8 @@ void spe_release_register(struct spe_function *p, int reg)
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const unsigned idx = reg / 64;
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const unsigned bit = reg % 64;
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assert(idx < 2);
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assert(reg < SPE_NUM_REGS);
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assert((p->regs[idx] & (1ULL << bit)) == 0);
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@ -458,4 +462,54 @@ EMIT_R (spe_mfspr, 0x00c);
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EMIT_R (spe_mtspr, 0x10c);
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#endif
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/**
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** Helper / "macro" instructions.
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** Use somewhat verbose names as a reminder that these aren't native
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** SPE instructions.
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**/
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void
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spe_load_float(struct spe_function *p, unsigned rT, float x)
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{
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union {
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float f;
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unsigned u;
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} bits;
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bits.f = x;
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spe_ilhu(p, rT, bits.u >> 16);
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spe_iohl(p, rT, bits.u & 0xffff);
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}
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void
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spe_load_int(struct spe_function *p, unsigned rT, int i)
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{
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spe_ilhu(p, rT, i >> 16);
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spe_iohl(p, rT, i & 0xffff);
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}
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void
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spe_complement(struct spe_function *p, unsigned rT)
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{
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spe_nor(p, rT, rT, rT);
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}
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void
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spe_move(struct spe_function *p, unsigned rT, unsigned rA)
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{
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spe_ori(p, rT, rA, 0);
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}
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void
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spe_zero(struct spe_function *p, unsigned rT)
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{
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spe_xor(p, rT, rT, rT);
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}
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#endif /* GALLIUM_CELL */
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@ -25,6 +25,7 @@
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/**
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* \file
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* Real-time assembly generation interface for Cell B.E. SPEs.
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* For details, see /opt/cell/sdk/docs/arch/SPU_ISA_v1.2_27Jan2007_pub.pdf
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*
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* \author Ian Romanick <idr@us.ibm.com>
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*/
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@ -38,11 +39,18 @@
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/** number of general-purpose SIMD registers */
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#define SPE_NUM_REGS 128
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/** Return Address register */
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#define SPE_REG_RA 0
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/** Stack Pointer register */
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#define SPE_REG_SP 1
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struct spe_function
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{
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uint32_t *store; /**< instruction buffer */
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uint32_t *csr; /**< next free pos in instruction buffer */
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const char *fn; /**< unused */
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uint32_t *store; /**< instruction buffer */
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uint num_inst;
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uint max_inst;
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/**
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* Mask of used / unused registers
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@ -123,7 +131,8 @@ EMIT_RI16(spe_ilhu, 0x082);
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EMIT_RI16(spe_il, 0x081);
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EMIT_RI18(spe_ila, 0x021);
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EMIT_RI16(spe_iohl, 0x0c1);
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EMIT_RI16(spe_fsmbi, 0x0c5);
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EMIT_RI16(spe_fsmbi, 0x065);
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/* Integer and logical instructions
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@ -275,6 +284,27 @@ extern void spe_bihnz(struct spe_function *p, unsigned rT, unsigned rA,
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int d, int e);
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/** Load/splat immediate float into rT. */
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extern void
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spe_load_float(struct spe_function *p, unsigned rT, float x);
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/** Load/splat immediate int into rT. */
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extern void
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spe_load_int(struct spe_function *p, unsigned rT, int i);
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/** Complement/invert all bits in rT. */
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extern void
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spe_complement(struct spe_function *p, unsigned rT);
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/** rT = rA. */
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extern void
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spe_move(struct spe_function *p, unsigned rT, unsigned rA);
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/** rT = {0,0,0,0}. */
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extern void
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spe_zero(struct spe_function *p, unsigned rT);
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/* Floating-point instructions
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*/
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EMIT_RR (spe_fa, 0x2c4);
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