pvr: Update for firmware 1.17@6256262
Signed-off-by: Sarah Walker <sarah.walker@imgtec.com> Reviewed-by: Frank Binns <frank.binns@imgtec.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17139>
This commit is contained in:
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ee9c3d2625
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ee491967c3
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@ -154,25 +154,37 @@ struct rogue_fwif_ta_regs {
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uint64_t vdm_ctrl_stream_base;
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uint64_t vdm_ctrl_stream_base;
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uint64_t tpu_border_colour_table;
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uint64_t tpu_border_colour_table;
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/* Only used when feature VDM_DRAWINDIRECT present. */
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uint64_t vdm_draw_indirect0;
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/* Only used when feature VDM_DRAWINDIRECT present. */
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uint32_t vdm_draw_indirect1;
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uint32_t ppp_ctrl;
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uint32_t ppp_ctrl;
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uint32_t te_psg;
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uint32_t te_psg;
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/* FIXME: HIGH: FIX_HW_BRN_49927 changes the structure's layout, given we
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/* Only used when BRN 49927 present. */
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* are supporting Features/ERNs/BRNs at runtime, we need to look into this
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* and find a solution to keep layout intact.
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*/
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/* Available if FIX_HW_BRN_49927 is present. */
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uint32_t tpu;
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uint32_t tpu;
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uint32_t vdm_context_resume_task0_size;
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uint32_t vdm_context_resume_task0_size;
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/* Only used when feature VDM_OBJECT_LEVEL_LLS present. */
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uint32_t vdm_context_resume_task3_size;
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/* FIXME: HIGH: FIX_HW_BRN_56279 changes the structure's layout, given we
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/* Only used when BRN 56279 or BRN 67381 present. */
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* are supporting Features/ERNs/BRNs at runtime, we need to look into this
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* and find a solution to keep layout intact.
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*/
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/* Available if FIX_HW_BRN_56279 is present. */
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uint32_t pds_ctrl;
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uint32_t pds_ctrl;
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uint32_t view_idx;
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uint32_t view_idx;
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/* Only used when feature TESSELLATION present */
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uint32_t pds_coeff_free_prog;
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uint32_t padding;
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};
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/**
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* \brief Dummy region header registers.
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*/
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/* Only used when BRN 44455 or BRN 63027 present. */
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struct rogue_fwif_dummy_rgnhdr_init_geom_regs {
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uint64_t te_psgregion_addr;
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};
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};
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/**
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/**
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@ -203,6 +215,15 @@ struct rogue_fwif_cmd_ta {
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* to go through.
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* to go through.
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*/
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*/
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struct rogue_fwif_ufo partial_render_ta_3d_fence;
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struct rogue_fwif_ufo partial_render_ta_3d_fence;
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/* Only used when BRN 44455 or BRN 63027 present. */
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struct rogue_fwif_dummy_rgnhdr_init_geom_regs
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ALIGN_ATTR(8) dummy_rgnhdr_init_geom_regs;
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/* Only used when BRN 61484 or BRN 66333 present. */
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uint32_t brn61484_66333_live_rt;
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uint32_t padding;
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};
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};
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static_assert(
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static_assert(
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@ -224,38 +245,34 @@ struct rogue_fwif_3d_regs {
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* section.
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* section.
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*/
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*/
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uint32_t usc_pixel_output_ctrl;
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uint32_t usc_pixel_output_ctrl;
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/* FIXME: HIGH: RGX_MAXIMUM_OUTPUT_REGISTERS_PER_PIXEL changes the
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* structure's layout.
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*/
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#define ROGUE_MAXIMUM_OUTPUT_REGISTERS_PER_PIXEL 8U
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#define ROGUE_MAXIMUM_OUTPUT_REGISTERS_PER_PIXEL 8U
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uint32_t usc_clear_register[ROGUE_MAXIMUM_OUTPUT_REGISTERS_PER_PIXEL];
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uint32_t usc_clear_register[ROGUE_MAXIMUM_OUTPUT_REGISTERS_PER_PIXEL];
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uint32_t isp_bgobjdepth;
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uint32_t isp_bgobjdepth;
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uint32_t isp_bgobjvals;
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uint32_t isp_bgobjvals;
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uint32_t isp_aa;
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uint32_t isp_aa;
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/* Only used when feature S7_TOP_INFRASTRUCTURE present. */
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uint32_t isp_xtp_pipe_enable;
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uint32_t isp_ctl;
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uint32_t isp_ctl;
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/* FIXME: HIGH: FIX_HW_BRN_49927 changes the structure's layout, given we
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/* Only used when feature CLUSTER_GROUPING present. */
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* are supporting Features/ERNs/BRNs at runtime, we need to look into this
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* and find a solution to keep layout intact.
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*/
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/* Available if FIX_HW_BRN_49927 is present. */
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uint32_t tpu;
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uint32_t tpu;
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uint32_t event_pixel_pds_info;
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uint32_t event_pixel_pds_info;
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/* FIXME: HIGH: RGX_FEATURE_CLUSTER_GROUPING changes the structure's
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* layout.
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*/
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uint32_t pixel_phantom;
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uint32_t pixel_phantom;
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uint32_t view_idx;
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uint32_t view_idx;
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uint32_t event_pixel_pds_data;
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uint32_t event_pixel_pds_data;
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/* FIXME: HIGH: MULTIBUFFER_OCLQRY changes the structure's layout.
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* Commenting out for now as it's not supported by 4.V.2.51.
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/* Only used when BRN 65101 present. */
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*/
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uint32_t brn65101_event_pixel_pds_data;
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/* uint32_t isp_oclqry_stride; */
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/* Only used when feature GPU_MULTICORE_SUPPORT or BRN 47217 present. */
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uint32_t isp_oclqry_stride;
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/* All values below the ALIGN_ATTR(8) must be 64 bit. */
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/* All values below the ALIGN_ATTR(8) must be 64 bit. */
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uint64_t ALIGN_ATTR(8) isp_scissor_base;
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uint64_t ALIGN_ATTR(8) isp_scissor_base;
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@ -264,22 +281,40 @@ struct rogue_fwif_3d_regs {
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uint64_t isp_zlsctl;
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uint64_t isp_zlsctl;
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uint64_t isp_zload_store_base;
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uint64_t isp_zload_store_base;
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uint64_t isp_stencil_load_store_base;
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uint64_t isp_stencil_load_store_base;
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/* FIXME: HIGH: RGX_FEATURE_ZLS_SUBTILE changes the structure's layout. */
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/* Only used when feature ZLS_SUBTILE present. */
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uint64_t isp_zls_pixels;
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uint64_t isp_zls_pixels;
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/* FIXME: HIGH: RGX_HW_REQUIRES_FB_CDC_ZLS_SETUP changes the structure's
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/*
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* layout.
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* Only used when feature FBCDC_ALGORITHM present and value < 3 or feature
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* FB_CDC_V4 present. Additionally, BRNs 48754, 60227, 72310 and 72311 must
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* not be present.
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*/
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*/
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uint64_t deprecated;
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uint64_t fb_cdc_zls;
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/* FIXME: HIGH: RGX_PBE_WORDS_REQUIRED_FOR_RENDERS changes the structure's
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#define ROGUE_PBE_WORDS_REQUIRED_FOR_RENDERS 3U
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* layout.
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*/
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#define ROGUE_PBE_WORDS_REQUIRED_FOR_RENDERS 2U
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uint64_t pbe_word[8U][ROGUE_PBE_WORDS_REQUIRED_FOR_RENDERS];
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uint64_t pbe_word[8U][ROGUE_PBE_WORDS_REQUIRED_FOR_RENDERS];
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uint64_t tpu_border_colour_table;
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uint64_t tpu_border_colour_table;
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uint64_t pds_bgnd[3U];
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uint64_t pds_bgnd[3U];
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/* Only used when BRN 65101 present. */
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uint64_t pds_bgnd_brn65101[3U];
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uint64_t pds_pr_bgnd[3U];
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uint64_t pds_pr_bgnd[3U];
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/* Only used when feature ISP_ZLS_D24_S8_PACKING_OGL_MODE present. */
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uint64_t rgx_cr_blackpearl_fix;
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/* Only used when BRN 62850 or 62865 present. */
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uint64_t isp_dummy_stencil_store_base;
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/* Only used when BRN 66193 present. */
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uint64_t isp_dummy_depth_store_base;
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/* Only used when BRN 67182 present. */
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uint32_t rgnhdr_single_rt_size;
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/* Only used when BRN 67182 present. */
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uint32_t rgnhdr_scratch_offset;
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};
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};
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/**
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/**
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@ -305,11 +340,17 @@ struct rogue_fwif_cmd_3d {
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/** Stride IN BYTES for S-Buffer in case of RTAs. */
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/** Stride IN BYTES for S-Buffer in case of RTAs. */
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uint32_t sls_stride;
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uint32_t sls_stride;
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/* FIXME: HIGH: RGX_FEATURE_GPU_MULTICORE_SUPPORT changes the structure's
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/* Only used when SUPPORT_STRIP_RENDERING present. */
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* layout. Commenting out for now as it's not supported by 4.V.2.51.
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uint8_t ui8FrameStripBuffer;
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*/
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/* Only used when SUPPORT_STRIP_RENDERING present. */
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uint8_t ui8FrameStripIndex;
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/* Only used when SUPPORT_STRIP_RENDERING present. */
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uint8_t ui8FrameStripMode;
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/* Number of tiles to submit to GPU<N> before moving to GPU<N+1>. */
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/* Number of tiles to submit to GPU<N> before moving to GPU<N+1>. */
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/* uint32_t execute_count; */
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uint32_t execute_count;
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uint32_t padding;
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};
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};
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static_assert(
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static_assert(
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@ -426,26 +467,36 @@ struct rogue_fwif_cmd_abort {
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struct rogue_fwif_cdm_regs {
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struct rogue_fwif_cdm_regs {
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uint64_t tpu_border_colour_table;
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uint64_t tpu_border_colour_table;
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/* FIXME: HIGH: RGX_FEATURE_COMPUTE_MORTON_CAPABLE changes the structure's
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/* Only used when feature COMPUTE_MORTON_CAPABLE present. */
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* layout.
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*/
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uint64_t cdm_item;
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uint64_t cdm_item;
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/* FIXME: HIGH: RGX_FEATURE_CLUSTER_GROUPING changes the structure's layout.
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*/
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/* Only used when feature CLUSTER_GROUPING present. */
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uint64_t compute_cluster;
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uint64_t compute_cluster;
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/* FIXME: HIGH: RGX_FEATURE_TPU_DM_GLOBAL_REGISTERS changes the structure's
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/* Only used when feature TPU_DM_GLOBAL_REGISTERS present. */
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* layout. Commenting out for now as it's not supported by 4.V.2.51.
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uint64_t tpu_tag_cdm_ctrl;
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*/
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/* uint64_t tpu_tag_cdm_ctrl; */
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uint64_t cdm_ctrl_stream_base;
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uint64_t cdm_contex_state_base_addr;
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/* FIXME: HIGH: FIX_HW_BRN_49927 changes the structure's layout, given we
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/* Only used when feature CDM_USER_MODE_QUEUE present. */
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* are supporting Features/ERNs/BRNs at runtime, we need to look into this
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uint64_t cdm_cb_queue;
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* and find a solution to keep layout intact.
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/*
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* Only used when feature CDM_USER_MODE_QUEUE is present and
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* SUPPORT_TRUSTED_DEVICE is present and SUPPORT_SECURE_ALLOC_KM is not
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* present.
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*/
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*/
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/* Available if FIX_HW_BRN_49927 is present. */
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uint64_t cdm_cb_secure_queue;
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/* Only used when feature CDM_USER_MODE_QUEUE present. */
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uint64_t cdm_cb_base;
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/* Only used when feature CDM_USER_MODE_QUEUE present. */
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uint64_t cdm_cb;
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/* Only used when feature CDM_USER_MODE_QUEUE is not present. */
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uint64_t cdm_ctrl_stream_base;
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uint64_t cdm_context_state_base_addr;
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/* Only used when BRN 49927 is present. */
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uint32_t tpu;
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uint32_t tpu;
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uint32_t cdm_resume_pds1;
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uint32_t cdm_resume_pds1;
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@ -462,11 +513,15 @@ struct rogue_fwif_cmd_compute {
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struct rogue_fwif_cdm_regs ALIGN_ATTR(8) regs;
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struct rogue_fwif_cdm_regs ALIGN_ATTR(8) regs;
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uint32_t ALIGN_ATTR(8) flags;
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uint32_t ALIGN_ATTR(8) flags;
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/* FIXME: HIGH: RGX_FEATURE_GPU_MULTICORE_SUPPORT changes the structure's
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/* Only used when feature UNIFIED_STORE_VIRTUAL_PARTITIONING present. */
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* layout. Commenting out for now as it's not supported by 4.V.2.51.
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uint32_t num_temp_regions;
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*/
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/* Only used when feature CDM_USER_MODE_QUEUE present. */
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uint32_t stream_start_offset;
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/* Number of tiles to submit to GPU<N> before moving to GPU<N+1>. */
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/* Number of tiles to submit to GPU<N> before moving to GPU<N+1>. */
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/* uint32_t execute_count; */
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/* Only used when feature GPU_MULTICORE_SUPPORT present. */
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uint32_t execute_count;
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};
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};
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static_assert(
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static_assert(
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@ -35,6 +35,8 @@
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#define ROGUE_FWIF_NUM_RTDATA_FREELISTS 2U
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#define ROGUE_FWIF_NUM_RTDATA_FREELISTS 2U
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#define ROGUE_NUM_GEOM_CORES 1U
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#define ROGUE_NUM_GEOM_CORES 1U
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#define ROGUE_NUM_GEOM_CORES_SIZE 2U
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/**
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/**
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* Maximum number of UFOs in a CCB command.
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* Maximum number of UFOs in a CCB command.
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* The number is based on having 32 sync prims (as originally), plus 32 sync
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* The number is based on having 32 sync prims (as originally), plus 32 sync
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struct rogue_fwif_dma_addr {
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struct rogue_fwif_dma_addr {
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uint64_t ALIGN_ATTR(8) dev_vaddr;
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uint64_t ALIGN_ATTR(8) dev_vaddr;
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struct rogue_fwif_dev_addr fw_addr;
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struct rogue_fwif_dev_addr fw_addr;
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uint32_t padding;
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} ALIGN_ATTR(8);
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} ALIGN_ATTR(8);
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/**
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/**
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@ -180,6 +183,16 @@ struct rogue_fwif_cccb_ctl {
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/** Offset wrapping mask, total capacity in bytes of the CCB-1. */
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/** Offset wrapping mask, total capacity in bytes of the CCB-1. */
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uint32_t wrap_mask;
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uint32_t wrap_mask;
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/* Only used if SUPPORT_AGP is present. */
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uint32_t read_offset2;
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/* Only used if SUPPORT_AGP4 is present. */
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uint32_t read_offset3;
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/* Only used if SUPPORT_AGP4 is present. */
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uint32_t read_offset4;
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uint32_t padding;
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} ALIGN_ATTR(8);
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} ALIGN_ATTR(8);
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#define ROGUE_FW_LOCAL_FREELIST 0U
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#define ROGUE_FW_LOCAL_FREELIST 0U
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@ -242,7 +255,7 @@ struct rogue_fwif_cdm_regs_cswitch {
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struct rogue_fwif_static_rendercontext_state {
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struct rogue_fwif_static_rendercontext_state {
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/** Geom registers for ctx switch. */
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/** Geom registers for ctx switch. */
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struct rogue_fwif_ta_regs_cswitch
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struct rogue_fwif_ta_regs_cswitch
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ALIGN_ATTR(8) ctx_switch_geom_regs[ROGUE_NUM_GEOM_CORES];
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ALIGN_ATTR(8) ctx_switch_geom_regs[ROGUE_NUM_GEOM_CORES_SIZE];
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};
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};
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#define ROGUE_FWIF_STATIC_RENDERCONTEXT_SIZE \
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#define ROGUE_FWIF_STATIC_RENDERCONTEXT_SIZE \
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@ -150,7 +150,7 @@ static void pvr_srv_compute_cmd_init(
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fw_regs->cdm_item = submit_info->regs.cdm_item;
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fw_regs->cdm_item = submit_info->regs.cdm_item;
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fw_regs->compute_cluster = submit_info->regs.compute_cluster;
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fw_regs->compute_cluster = submit_info->regs.compute_cluster;
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fw_regs->cdm_ctrl_stream_base = submit_info->regs.cdm_ctrl_stream_base;
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fw_regs->cdm_ctrl_stream_base = submit_info->regs.cdm_ctrl_stream_base;
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fw_regs->cdm_contex_state_base_addr =
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fw_regs->cdm_context_state_base_addr =
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submit_info->regs.cdm_ctx_state_base_addr;
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submit_info->regs.cdm_ctx_state_base_addr;
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fw_regs->tpu = submit_info->regs.tpu;
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fw_regs->tpu = submit_info->regs.tpu;
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fw_regs->cdm_resume_pds1 = submit_info->regs.cdm_resume_pds1;
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fw_regs->cdm_resume_pds1 = submit_info->regs.cdm_resume_pds1;
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@ -295,8 +295,6 @@ static void pvr_srv_render_ctx_fw_static_state_init(
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||||||
struct rogue_fwif_ta_regs_cswitch *regs =
|
struct rogue_fwif_ta_regs_cswitch *regs =
|
||||||
&static_state->ctx_switch_geom_regs[0];
|
&static_state->ctx_switch_geom_regs[0];
|
||||||
|
|
||||||
STATIC_ASSERT(ARRAY_SIZE(static_state->ctx_switch_geom_regs) == 1);
|
|
||||||
|
|
||||||
memset(static_state, 0, sizeof(*static_state));
|
memset(static_state, 0, sizeof(*static_state));
|
||||||
|
|
||||||
regs->vdm_context_state_base_addr = ws_static_state->vdm_ctx_state_base_addr;
|
regs->vdm_context_state_base_addr = ws_static_state->vdm_ctx_state_base_addr;
|
||||||
|
|
Loading…
Reference in New Issue