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gallium/radeon: fix a ZPASS comment, EVENT_WRITE_EOP fixups 

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2016-10-03 15:13:56 +02:00
parent d883c83ba9
commit edf56fb428
3 changed files with 5 additions and 5 deletions
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2
src/amd/common/sid.h
View File

@ -7761,7 +7761,7 @@
#define V_028A90_FLUSH_HS_OUTPUT 0x11
#define V_028A90_FLUSH_LS_OUTPUT 0x12
#define V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT 0x14
#define V_028A90_ZPASS_DONE 0x15 /* not on CIK */
#define V_028A90_ZPASS_DONE 0x15
#define V_028A90_CACHE_FLUSH_AND_INV_EVENT 0x16
#define V_028A90_PERFCOUNTER_START 0x17
#define V_028A90_PERFCOUNTER_STOP 0x18

4
src/gallium/drivers/radeon/r600_pipe_common.c
View File

@ -94,7 +94,7 @@ void r600_gfx_write_fence(struct r600_common_context *ctx, struct r600_resource
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
EVENT_INDEX(5));
radeon_emit(cs, va);
radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(1));
radeon_emit(cs, old_value); /* immediate data */
radeon_emit(cs, 0); /* unused */
}
@ -103,7 +103,7 @@ void r600_gfx_write_fence(struct r600_common_context *ctx, struct r600_resource
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
EVENT_INDEX(5));
radeon_emit(cs, va);
radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(1));
radeon_emit(cs, new_value); /* immediate data */
radeon_emit(cs, 0); /* unused */

4
src/gallium/drivers/radeon/r600_query.c
View File

@ -560,7 +560,7 @@ static void r600_query_hw_do_emit_start(struct r600_common_context *ctx,
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) | EVENT_INDEX(5));
radeon_emit(cs, va);
radeon_emit(cs, (3 << 29) | ((va >> 32) & 0xFFFF));
radeon_emit(cs, EOP_DATA_SEL(3) | ((va >> 32) & 0xFFFF));
radeon_emit(cs, 0);
radeon_emit(cs, 0);
break;
@ -646,7 +646,7 @@ static void r600_query_hw_do_emit_stop(struct r600_common_context *ctx,
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) | EVENT_INDEX(5));
radeon_emit(cs, va);
radeon_emit(cs, (3 << 29) | ((va >> 32) & 0xFFFF));
radeon_emit(cs, EOP_DATA_SEL(3) | ((va >> 32) & 0xFFFF));
radeon_emit(cs, 0);
radeon_emit(cs, 0);