radeonsi: add performance thresholds for CP DMA, decrease it for clears
The first one isn't used yet. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
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@ -28,6 +28,12 @@
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#include "sid.h"
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#include "sid.h"
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#include "radeon/r600_cs.h"
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#include "radeon/r600_cs.h"
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/* Recommended maximum sizes for optimal performance.
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* Fall back to compute or SDMA if the size is greater.
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*/
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#define CP_DMA_COPY_PERF_THRESHOLD (64 * 1024) /* copied from Vulkan */
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#define CP_DMA_CLEAR_PERF_THRESHOLD (32 * 1024) /* guess (clear is much slower) */
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/* Set this if you want the ME to wait until CP DMA is done.
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/* Set this if you want the ME to wait until CP DMA is done.
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* It should be set on the last CP DMA packet. */
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* It should be set on the last CP DMA packet. */
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#define CP_DMA_SYNC (1 << 0)
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#define CP_DMA_SYNC (1 << 0)
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@ -230,7 +236,7 @@ static void si_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst,
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(offset % 4 == 0) &&
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(offset % 4 == 0) &&
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/* CP DMA is very slow. Always use SDMA for big clears. This
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/* CP DMA is very slow. Always use SDMA for big clears. This
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* alone improves DeusEx:MD performance by 70%. */
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* alone improves DeusEx:MD performance by 70%. */
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(size > 128 * 1024 ||
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(size > CP_DMA_CLEAR_PERF_THRESHOLD ||
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/* Buffers not used by the GFX IB yet will be cleared by SDMA.
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/* Buffers not used by the GFX IB yet will be cleared by SDMA.
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* This happens to move most buffer clears to SDMA, including
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* This happens to move most buffer clears to SDMA, including
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* DCC and CMASK clears, because pipe->clear clears them before
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* DCC and CMASK clears, because pipe->clear clears them before
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