radv: clean up radv_vi_dcc_enabled()
And rename to radv_dcc_enabled() to be consistent. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
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@ -3560,7 +3560,7 @@ radv_initialise_color_surface(struct radv_device *device,
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!(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
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cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
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if (radv_vi_dcc_enabled(iview->image, iview->base_mip))
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if (radv_dcc_enabled(iview->image, iview->base_mip))
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cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
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if (device->physical_device->rad_info.chip_class >= VI) {
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@ -294,7 +294,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
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if (chip_class >= VI) {
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state[6] &= C_008F28_COMPRESSION_EN;
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state[7] = 0;
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if (!is_storage_image && radv_vi_dcc_enabled(image, first_level)) {
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if (!is_storage_image && radv_dcc_enabled(image, first_level)) {
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meta_va = gpu_address + image->dcc_offset;
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if (chip_class <= VI)
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meta_va += base_level_info->dcc_offset;
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@ -1384,12 +1384,6 @@ bool radv_layout_dcc_compressed(const struct radv_image *image,
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VkImageLayout layout,
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unsigned queue_mask);
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static inline bool
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radv_vi_dcc_enabled(const struct radv_image *image, unsigned level)
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{
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return image->surface.dcc_size && level < image->surface.num_dcc_levels;
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}
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/**
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* Return whether the image has CMASK metadata for color surfaces.
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*/
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@ -1417,6 +1411,16 @@ radv_image_has_dcc(const struct radv_image *image)
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return image->surface.dcc_size;
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}
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/**
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* Return whether DCC metadata is enabled for a level.
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*/
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static inline bool
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radv_dcc_enabled(const struct radv_image *image, unsigned level)
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{
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return radv_image_has_dcc(image) &&
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level < image->surface.num_dcc_levels;
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}
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/**
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* Return whether the image has HTILE metadata for depth surfaces.
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*/
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