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r600g,radeonsi: add debug flags which disable tiling 

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Marek Olšák 2014-07-25 23:06:18 +02:00
parent 04f2c88f45
commit ecbd3a545a
3 changed files with 24 additions and 13 deletions
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6
src/gallium/drivers/radeon/r600_pipe_common.c
View File

@ -233,8 +233,6 @@ static const struct debug_named_value common_debug_options[] = {
{ "vm", DBG_VM, "Print virtual addresses when creating resources" },
{ "trace_cs", DBG_TRACE_CS, "Trace cs and write rlockup_<csid>.c file with faulty cs" },
/* features */
{ "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
/* shaders */
{ "fs", DBG_FS, "Print fetch shaders" },
@ -243,9 +241,13 @@ static const struct debug_named_value common_debug_options[] = {
{ "ps", DBG_PS, "Print pixel shaders" },
{ "cs", DBG_CS, "Print compute shaders" },
/* features */
{ "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
{ "hyperz", DBG_HYPERZ, "Enable Hyper-Z" },
/* GL uses the word INVALIDATE, gallium uses the word DISCARD */
{ "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
{ "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
{ "notiling", DBG_NO_TILING, "Disable tiling" },
DEBUG_NAMED_VALUE_END /* must be last */
};

21
src/gallium/drivers/radeon/r600_pipe_common.h
View File

@ -80,17 +80,18 @@
#define DBG_COMPUTE (1 << 2)
#define DBG_VM (1 << 3)
#define DBG_TRACE_CS (1 << 4)
/* shader logging */
#define DBG_FS (1 << 5)
#define DBG_VS (1 << 6)
#define DBG_GS (1 << 7)
#define DBG_PS (1 << 8)
#define DBG_CS (1 << 9)
/* features */
#define DBG_NO_ASYNC_DMA (1 << 5)
/* shaders */
#define DBG_FS (1 << 8)
#define DBG_VS (1 << 9)
#define DBG_GS (1 << 10)
#define DBG_PS (1 << 11)
#define DBG_CS (1 << 12)
/* features */
#define DBG_HYPERZ (1 << 13)
#define DBG_NO_DISCARD_RANGE (1 << 14)
#define DBG_NO_ASYNC_DMA (1 << 10)
#define DBG_HYPERZ (1 << 11)
#define DBG_NO_DISCARD_RANGE (1 << 12)
#define DBG_NO_2D_TILING (1 << 13)
#define DBG_NO_TILING (1 << 14)
/* The maximum allowed bit is 15. */
#define R600_MAP_BUFFER_ALIGNMENT 64

10
src/gallium/drivers/radeon/r600_texture.c
View File

@ -737,6 +737,13 @@ static unsigned r600_choose_tiling(struct r600_common_screen *rscreen,
* Compressed textures must always be tiled. */
if (!(templ->flags & R600_RESOURCE_FLAG_FORCE_TILING) &&
!util_format_is_compressed(templ->format)) {
/* Not everything can be linear, so we cannot enforce it
* for all textures. */
if ((rscreen->debug_flags & DBG_NO_TILING) &&
(!util_format_is_depth_or_stencil(templ->format) ||
!(templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH)))
return RADEON_SURF_MODE_LINEAR_ALIGNED;
/* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED)
return RADEON_SURF_MODE_LINEAR_ALIGNED;
@ -763,7 +770,8 @@ static unsigned r600_choose_tiling(struct r600_common_screen *rscreen,
}
/* Make small textures 1D tiled. */
if (templ->width0 <= 16 || templ->height0 <= 16)
if (templ->width0 <= 16 || templ->height0 <= 16 ||
(rscreen->debug_flags & DBG_NO_2D_TILING))
return RADEON_SURF_MODE_1D;
/* The allocator will switch to 1D if needed. */