radeon/llvm: Coding style fixes for R600CodeEmitter.cpp
This commit is contained in:
Tom Stellard
parent
224e187f98
commit
ec201667bf
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@ -38,16 +38,15 @@ using namespace llvm;
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namespace {
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class R600CodeEmitter : public MachineFunctionPass, public AMDILCodeEmitter {
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class R600CodeEmitter : public MachineFunctionPass, public AMDILCodeEmitter {
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private:
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private:
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static char ID;
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formatted_raw_ostream &_OS;
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const TargetMachine * TM;
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const MachineRegisterInfo * MRI;
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const R600RegisterInfo * TRI;
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bool evergreenEncoding;
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bool isCube;
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bool isReduction;
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@ -56,10 +55,10 @@ namespace {
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unsigned section_start;
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public:
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public:
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R600CodeEmitter(formatted_raw_ostream &OS) : MachineFunctionPass(ID),
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_OS(OS), TM(NULL), evergreenEncoding(false), isCube(false), isReduction(false),
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_OS(OS), TM(NULL), isCube(false), isReduction(false),
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isLast(true) { }
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const char *getPassName() const { return "AMDGPU Machine Code Emitter"; }
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@ -68,7 +67,7 @@ namespace {
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virtual uint64_t getMachineOpValue(const MachineInstr &MI,
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const MachineOperand &MO) const;
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private:
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private:
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void emitALUInstr(MachineInstr &MI);
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void emitSrc(const MachineOperand & MO, int chan_override = -1);
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@ -77,8 +76,6 @@ namespace {
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void emitTexInstr(MachineInstr &MI);
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void emitFCInstr(MachineInstr &MI);
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unsigned int getHWInst(const MachineInstr &MI);
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void emitNullBytes(unsigned int byteCount);
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void emitByte(unsigned int byte);
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@ -92,12 +89,7 @@ namespace {
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};
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} /* End anonymous namespace */
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#define WRITE_MASK_X 0x1
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#define WRITE_MASK_Y 0x2
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#define WRITE_MASK_Z 0x4
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#define WRITE_MASK_W 0x8
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} // End anonymous namespace
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enum RegElement {
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ELEMENT_X = 0,
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@ -128,14 +120,14 @@ enum FCInstr {
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enum TextureTypes {
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TEXTURE_1D = 1,
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TEXTURE_2D,
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TEXTURE_2D,
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TEXTURE_3D,
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TEXTURE_CUBE,
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TEXTURE_RECT,
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TEXTURE_SHADOW1D,
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TEXTURE_SHADOW2D,
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TEXTURE_SHADOWRECT,
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TEXTURE_1D_ARRAY,
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TEXTURE_SHADOWRECT,
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TEXTURE_1D_ARRAY,
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TEXTURE_2D_ARRAY,
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TEXTURE_SHADOW1D_ARRAY,
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TEXTURE_SHADOW2D_ARRAY
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@ -154,11 +146,6 @@ bool R600CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
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TRI = static_cast<const R600RegisterInfo *>(TM->getRegisterInfo());
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const AMDILSubtarget &STM = TM->getSubtarget<AMDILSubtarget>();
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std::string gpu = STM.getDeviceName();
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if (!gpu.compare(0,3, "rv7")) {
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evergreenEncoding = false;
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} else {
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evergreenEncoding = true;
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}
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if (STM.dumpCode()) {
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MF.dump();
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@ -202,10 +189,10 @@ bool R600CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
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case AMDIL::RAT_WRITE_CACHELESS_eg:
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{
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uint64_t inst = getBinaryCodeForInstr(MI);
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/* Set End Of Program bit */
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/* XXX: Need better check of end of program. EOP should be
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* encoded in one of the operands of the MI, and it should be
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* set in a prior pass. */
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// Set End Of Program bit
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// XXX: Need better check of end of program. EOP should be
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// encoded in one of the operands of the MI, and it should be
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// set in a prior pass.
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MachineBasicBlock::iterator NextI = llvm::next(I);
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MachineInstr &NextMI = *NextI;
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if (NextMI.getOpcode() == AMDIL::RETURN) {
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@ -218,58 +205,58 @@ bool R600CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
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case AMDIL::VTX_READ_eg:
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{
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emitByte(INSTR_VTX);
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/* inst */
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// inst
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emitByte(0);
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/* fetch_type */
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// fetch_type
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emitByte(2);
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/* buffer_id */
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// buffer_id
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emitByte(MI.getOperand(2).getImm());
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/* src_gpr */
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// src_gpr
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emitByte(getHWReg(MI.getOperand(1).getReg()));
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/* src_sel_x */
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// src_sel_x
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emitByte(TRI->getHWRegChan(MI.getOperand(1).getReg()));
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/* mega_fetch_count */
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// mega_fetch_count
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emitByte(3);
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/* dst_gpr */
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// dst_gpr
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emitByte(getHWReg(MI.getOperand(0).getReg()));
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/* dst_sel_x */
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// dst_sel_x
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emitByte(0);
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/* dst_sel_y */
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// dst_sel_y
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emitByte(7);
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/* dst_sel_z */
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// dst_sel_z
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emitByte(7);
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/* dst_sel_w */
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// dst_sel_w
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emitByte(7);
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/* use_const_fields */
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// use_const_fields
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emitByte(1);
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/* data_format */
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// data_format
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emitByte(0);
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/* num_format_all */
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// num_format_all
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emitByte(0);
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/* format_comp_all */
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// format_comp_all
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emitByte(0);
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/* srf_mode_all */
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// srf_mode_all
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emitByte(0);
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/* offset */
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// offset
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emitByte(0);
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/* endian */
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// endian
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emitByte(0);
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break;
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}
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@ -289,29 +276,19 @@ void R600CodeEmitter::emitALUInstr(MachineInstr &MI)
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unsigned numOperands = MI.getNumExplicitOperands();
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/* Some instructions are just place holder instructions that represent
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* operations that the GPU does automatically. They should be ignored. */
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// Some instructions are just place holder instructions that represent
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// operations that the GPU does automatically. They should be ignored.
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if (AMDGPU::isPlaceHolderOpcode(MI.getOpcode())) {
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return;
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}
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/* We need to handle some opcodes differently */
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switch (MI.getOpcode()) {
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default: break;
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/* XXX: Temp Hack */
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case AMDIL::STORE_OUTPUT:
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numOperands = 2;
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break;
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}
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/* XXX Check if instruction writes a result */
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// XXX Check if instruction writes a result
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if (numOperands < 1) {
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return;
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}
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const MachineOperand dstOp = MI.getOperand(0);
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/* Emit instruction type */
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// Emit instruction type
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emitByte(0);
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if (isCube) {
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@ -322,14 +299,14 @@ void R600CodeEmitter::emitALUInstr(MachineInstr &MI)
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} else {
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unsigned int opIndex;
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for (opIndex = 1; opIndex < numOperands; opIndex++) {
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/* Literal constants are always stored as the last operand. */
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// Literal constants are always stored as the last operand.
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if (MI.getOperand(opIndex).isImm() || MI.getOperand(opIndex).isFPImm()) {
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break;
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}
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emitSrc(MI.getOperand(opIndex));
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}
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/* Emit zeros for unused sources */
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// Emit zeros for unused sources
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for ( ; opIndex < 4; opIndex++) {
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emitNullBytes(SRC_BYTE_COUNT);
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}
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@ -340,12 +317,12 @@ void R600CodeEmitter::emitALUInstr(MachineInstr &MI)
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emitALU(MI, numOperands - 1);
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}
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void R600CodeEmitter::emitSrc(const MachineOperand & MO, int chan_override /* = -1 */)
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void R600CodeEmitter::emitSrc(const MachineOperand & MO, int chan_override)
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{
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uint32_t value = 0;
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/* Emit the source select (2 bytes). For GPRs, this is the register index.
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* For other potential instruction operands, (e.g. constant registers) the
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* value of the source select is defined in the r600isa docs. */
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// Emit the source select (2 bytes). For GPRs, this is the register index.
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// For other potential instruction operands, (e.g. constant registers) the
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// value of the source select is defined in the r600isa docs.
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if (MO.isReg()) {
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unsigned reg = MO.getReg();
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emitTwoBytes(getHWReg(reg));
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@ -361,11 +338,11 @@ void R600CodeEmitter::emitSrc(const MachineOperand & MO, int chan_override /* =
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}
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}
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} else {
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/* XXX: Handle other operand types. */
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// XXX: Handle other operand types.
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emitTwoBytes(0);
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}
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/* Emit the source channel (1 byte) */
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// Emit the source channel (1 byte)
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if (chan_override != -1) {
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emitByte(chan_override);
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} else if (isReduction) {
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@ -376,7 +353,7 @@ void R600CodeEmitter::emitSrc(const MachineOperand & MO, int chan_override /* =
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emitByte(0);
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}
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/* XXX: Emit isNegated (1 byte) */
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// XXX: Emit isNegated (1 byte)
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if ((!(MO.getTargetFlags() & MO_FLAG_ABS))
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&& (MO.getTargetFlags() & MO_FLAG_NEG ||
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(MO.isReg() &&
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@ -386,20 +363,20 @@ void R600CodeEmitter::emitSrc(const MachineOperand & MO, int chan_override /* =
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emitByte(0);
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}
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/* Emit isAbsolute (1 byte) */
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// Emit isAbsolute (1 byte)
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if (MO.getTargetFlags() & MO_FLAG_ABS) {
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emitByte(1);
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} else {
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emitByte(0);
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}
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/* XXX: Emit relative addressing mode (1 byte) */
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// XXX: Emit relative addressing mode (1 byte)
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emitByte(0);
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/* Emit kc_bank, This will be adjusted later by r600_asm */
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// Emit kc_bank, This will be adjusted later by r600_asm
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emitByte(0);
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/* Emit the literal value, if applicable (4 bytes). */
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// Emit the literal value, if applicable (4 bytes).
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emit(value);
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}
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@ -407,24 +384,24 @@ void R600CodeEmitter::emitSrc(const MachineOperand & MO, int chan_override /* =
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void R600CodeEmitter::emitDst(const MachineOperand & MO)
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{
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if (MO.isReg()) {
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/* Emit the destination register index (1 byte) */
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// Emit the destination register index (1 byte)
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emitByte(getHWReg(MO.getReg()));
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/* Emit the element of the destination register (1 byte)*/
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// Emit the element of the destination register (1 byte)
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if (isReduction || isCube) {
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emitByte(currentElement);
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} else {
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emitByte(TRI->getHWRegChan(MO.getReg()));
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}
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/* Emit isClamped (1 byte) */
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// Emit isClamped (1 byte)
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if (MO.getTargetFlags() & MO_FLAG_CLAMP) {
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emitByte(1);
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} else {
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emitByte(0);
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}
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/* Emit writemask (1 byte). */
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// Emit writemask (1 byte).
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if ((isReduction && currentElement != TRI->getHWRegChan(MO.getReg()))
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|| MO.getTargetFlags() & MO_FLAG_MASK) {
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emitByte(0);
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@ -432,47 +409,47 @@ void R600CodeEmitter::emitDst(const MachineOperand & MO)
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emitByte(1);
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}
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/* XXX: Emit relative addressing mode */
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// XXX: Emit relative addressing mode
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emitByte(0);
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} else {
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/* XXX: Handle other operand types. Are there any for destination regs? */
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// XXX: Handle other operand types. Are there any for destination regs?
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emitNullBytes(DST_BYTE_COUNT);
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}
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}
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void R600CodeEmitter::emitALU(MachineInstr &MI, unsigned numSrc)
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{
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/* Emit the instruction (2 bytes) */
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emitTwoBytes(getHWInst(MI));
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// Emit the instruction (2 bytes)
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emitTwoBytes(getBinaryCodeForInstr(MI));
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/* Emit isLast (for this instruction group) (1 byte) */
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// Emit isLast (for this instruction group) (1 byte)
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if (isLast) {
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emitByte(1);
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} else {
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emitByte(0);
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}
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/* Emit isOp3 (1 byte) */
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// Emit isOp3 (1 byte)
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if (numSrc == 3) {
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emitByte(1);
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} else {
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emitByte(0);
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}
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/* XXX: Emit predicate (1 byte) */
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// XXX: Emit predicate (1 byte)
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emitByte(0);
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/* XXX: Emit bank swizzle. (1 byte) Do we need this? It looks like
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* r600_asm.c sets it. */
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// XXX: Emit bank swizzle. (1 byte) Do we need this? It looks like
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// r600_asm.c sets it.
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emitByte(0);
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/* XXX: Emit bank_swizzle_force (1 byte) Not sure what this is for. */
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// XXX: Emit bank_swizzle_force (1 byte) Not sure what this is for.
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emitByte(0);
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/* XXX: Emit OMOD (1 byte) Not implemented. */
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// XXX: Emit OMOD (1 byte) Not implemented.
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emitByte(0);
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/* XXX: Emit index_mode. I think this is for indirect addressing, so we
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* don't need to worry about it. */
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// XXX: Emit index_mode. I think this is for indirect addressing, so we
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// don't need to worry about it.
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emitByte(0);
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}
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@ -484,37 +461,37 @@ void R600CodeEmitter::emitTexInstr(MachineInstr &MI)
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unsigned opcode = MI.getOpcode();
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unsigned srcSelect[4] = {0, 1, 2, 3};
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/* Emit instruction type */
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// Emit instruction type
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emitByte(1);
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/* Emit instruction */
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emitByte(getHWInst(MI));
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// Emit instruction
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emitByte(getBinaryCodeForInstr(MI));
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/* XXX: Emit resource id r600_shader.c uses sampler + 1. Why? */
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// XXX: Emit resource id r600_shader.c uses sampler + 1. Why?
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emitByte(sampler + 1 + 1);
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/* Emit source register */
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// Emit source register
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emitByte(getHWReg(MI.getOperand(1).getReg()));
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/* XXX: Emit src isRelativeAddress */
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// XXX: Emit src isRelativeAddress
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emitByte(0);
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/* Emit destination register */
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// Emit destination register
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emitByte(getHWReg(MI.getOperand(0).getReg()));
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/* XXX: Emit dst isRealtiveAddress */
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// XXX: Emit dst isRealtiveAddress
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emitByte(0);
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/* XXX: Emit dst select */
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emitByte(0); /* X */
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emitByte(1); /* Y */
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emitByte(2); /* Z */
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emitByte(3); /* W */
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// XXX: Emit dst select
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emitByte(0); // X
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emitByte(1); // Y
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emitByte(2); // Z
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emitByte(3); // W
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/* XXX: Emit lod bias */
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// XXX: Emit lod bias
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emitByte(0);
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/* XXX: Emit coord types */
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// XXX: Emit coord types
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unsigned coordType[4] = {1, 1, 1, 1};
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if (textureType == TEXTURE_RECT
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@ -540,16 +517,16 @@ void R600CodeEmitter::emitTexInstr(MachineInstr &MI)
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emitByte(coordType[i]);
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}
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/* XXX: Emit offsets */
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emitByte(0); /* X */
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emitByte(0); /* Y */
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emitByte(0); /* Z */
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/* There is no OFFSET_W */
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// XXX: Emit offsets
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emitByte(0); // X
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emitByte(0); // Y
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emitByte(0); // Z
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// There is no OFFSET_W
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/* Emit sampler id */
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// Emit sampler id
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emitByte(sampler);
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/* XXX:Emit source select */
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// XXX:Emit source select
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if ((textureType == TEXTURE_SHADOW1D
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|| textureType == TEXTURE_SHADOW2D
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|| textureType == TEXTURE_SHADOWRECT
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@ -566,10 +543,10 @@ void R600CodeEmitter::emitTexInstr(MachineInstr &MI)
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void R600CodeEmitter::emitFCInstr(MachineInstr &MI)
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{
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/* Emit instruction type */
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// Emit instruction type
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emitByte(INSTR_FC);
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/* Emit SRC */
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// Emit SRC
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unsigned numOperands = MI.getNumOperands();
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if (numOperands > 0) {
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assert(numOperands == 1);
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@ -578,7 +555,7 @@ void R600CodeEmitter::emitFCInstr(MachineInstr &MI)
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emitNullBytes(SRC_BYTE_COUNT);
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}
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/* Emit FC Instruction */
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// Emit FC Instruction
|
||||
enum FCInstr instr;
|
||||
switch (MI.getOpcode()) {
|
||||
case AMDIL::BREAK_LOGICALZ_f32:
|
||||
|
|
@ -595,8 +572,6 @@ void R600CodeEmitter::emitFCInstr(MachineInstr &MI)
|
|||
case AMDIL::CONTINUE_LOGICALNZ_i32:
|
||||
instr = FC_CONTINUE;
|
||||
break;
|
||||
/* XXX: This assumes that all IFs will be if (x != 0). If we add
|
||||
* optimizations this might not be the case */
|
||||
case AMDIL::IF_LOGICALNZ_f32:
|
||||
case AMDIL::IF_LOGICALNZ_i32:
|
||||
instr = FC_IF;
|
||||
|
|
@ -623,39 +598,6 @@ void R600CodeEmitter::emitFCInstr(MachineInstr &MI)
|
|||
emitByte(instr);
|
||||
}
|
||||
|
||||
#define INSTR_FLOAT2_V(inst, hw) \
|
||||
case AMDIL:: inst##_v4f32: \
|
||||
case AMDIL:: inst##_v2f32: return HW_INST2(hw);
|
||||
|
||||
#define INSTR_FLOAT2_S(inst, hw) \
|
||||
case AMDIL:: inst##_f32: return HW_INST2(hw);
|
||||
|
||||
#define INSTR_FLOAT2(inst, hw) \
|
||||
INSTR_FLOAT2_V(inst, hw) \
|
||||
INSTR_FLOAT2_S(inst, hw)
|
||||
|
||||
unsigned int R600CodeEmitter::getHWInst(const MachineInstr &MI)
|
||||
{
|
||||
|
||||
/* XXX: Lower these to MOV before the code emitter. */
|
||||
switch (MI.getOpcode()) {
|
||||
case AMDIL::STORE_OUTPUT:
|
||||
case AMDIL::VCREATE_v4i32:
|
||||
case AMDIL::LOADCONST_i32:
|
||||
case AMDIL::LOADCONST_f32:
|
||||
case AMDIL::MOVE_v4i32:
|
||||
/* Instructons to reinterpret bits as ... */
|
||||
case AMDIL::IL_ASINT_f32:
|
||||
case AMDIL::IL_ASINT_i32:
|
||||
case AMDIL::IL_ASFLOAT_f32:
|
||||
case AMDIL::IL_ASFLOAT_i32:
|
||||
return 0x19;
|
||||
|
||||
default:
|
||||
return getBinaryCodeForInstr(MI);
|
||||
}
|
||||
}
|
||||
|
||||
void R600CodeEmitter::emitNullBytes(unsigned int byteCount)
|
||||
{
|
||||
for (unsigned int i = 0; i < byteCount; i++) {
|
||||
|
|
|
|||
Loading…
Reference in New Issue