pan/mdg: Handle comparisons in fp16 path
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
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@ -578,15 +578,33 @@ nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
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broadcast_swizzle = count; \
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broadcast_swizzle = count; \
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assert(src_bitsize == dst_bitsize); \
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assert(src_bitsize == dst_bitsize); \
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break;
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break;
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/* Analyze the sizes of the inputs to determine which reg mode. Ops needed
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* special treatment override this anyway. */
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#define ALU_CHECK_CMP(sext) \
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if (src_bitsize == 16 && dst_bitsize == 32) { \
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half_1 = true; \
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half_2 = true; \
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sext_1 = sext; \
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sext_2 = sext; \
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} else { \
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assert(src_bitsize == dst_bitsize); \
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} \
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#define ALU_CASE_CMP(nir, _op, sext) \
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case nir_op_##nir: \
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op = midgard_alu_op_##_op; \
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ALU_CHECK_CMP(sext); \
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break;
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/* Analyze the sizes of the dest and inputs to determine reg mode. */
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static midgard_reg_mode
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static midgard_reg_mode
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reg_mode_for_nir(nir_alu_instr *instr)
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reg_mode_for_nir(nir_alu_instr *instr)
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{
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{
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unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
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unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
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unsigned dst_bitsize = nir_dest_bit_size(instr->dest.dest);
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unsigned max_bitsize = MAX2(src_bitsize, dst_bitsize);
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switch (src_bitsize) {
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switch (max_bitsize) {
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case 8:
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case 8:
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return midgard_reg_mode_8;
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return midgard_reg_mode_8;
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case 16:
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case 16:
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@ -782,13 +800,13 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
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ALU_CASE(mov, imov);
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ALU_CASE(mov, imov);
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ALU_CASE(feq32, feq);
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ALU_CASE_CMP(feq32, feq, false);
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ALU_CASE(fne32, fne);
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ALU_CASE_CMP(fne32, fne, false);
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ALU_CASE(flt32, flt);
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ALU_CASE_CMP(flt32, flt, false);
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ALU_CASE(ieq32, ieq);
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ALU_CASE_CMP(ieq32, ieq, true);
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ALU_CASE(ine32, ine);
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ALU_CASE_CMP(ine32, ine, true);
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ALU_CASE(ilt32, ilt);
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ALU_CASE_CMP(ilt32, ilt, true);
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ALU_CASE(ult32, ult);
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ALU_CASE_CMP(ult32, ult, false);
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/* We don't have a native b2f32 instruction. Instead, like many
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/* We don't have a native b2f32 instruction. Instead, like many
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* GPUs, we exploit booleans as 0/~0 for false/true, and
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* GPUs, we exploit booleans as 0/~0 for false/true, and
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@ -801,14 +819,14 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
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* At the end of emit_alu (as MIR), we'll fix-up the constant
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* At the end of emit_alu (as MIR), we'll fix-up the constant
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*/
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*/
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ALU_CASE(b2f32, iand);
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ALU_CASE_CMP(b2f32, iand, true);
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ALU_CASE(b2i32, iand);
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ALU_CASE_CMP(b2i32, iand, true);
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/* Likewise, we don't have a dedicated f2b32 instruction, but
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/* Likewise, we don't have a dedicated f2b32 instruction, but
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* we can do a "not equal to 0.0" test. */
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* we can do a "not equal to 0.0" test. */
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ALU_CASE(f2b32, fne);
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ALU_CASE_CMP(f2b32, fne, false);
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ALU_CASE(i2b32, ine);
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ALU_CASE_CMP(i2b32, ine, true);
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ALU_CASE(frcp, frcp);
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ALU_CASE(frcp, frcp);
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ALU_CASE(frsq, frsqrt);
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ALU_CASE(frsq, frsqrt);
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@ -899,9 +917,6 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
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if (dst_bitsize == (src_bitsize * 2)) {
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if (dst_bitsize == (src_bitsize * 2)) {
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/* Converting up */
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/* Converting up */
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half_2 = true;
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half_2 = true;
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/* Use a greater register mode */
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reg_mode++;
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} else if (src_bitsize == (dst_bitsize * 2)) {
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} else if (src_bitsize == (dst_bitsize * 2)) {
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/* Converting down */
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/* Converting down */
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dest_override = midgard_dest_override_lower;
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dest_override = midgard_dest_override_lower;
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@ -925,6 +940,7 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
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0;
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0;
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flip_src12 = true;
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flip_src12 = true;
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ALU_CHECK_CMP(false);
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break;
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break;
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}
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}
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