r600g: drop tiled flag
we can work this out from the array_mode and it makes more sense to do that. Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -390,10 +390,8 @@ static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_conte
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bo[1] = rbuffer->bo;
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pitch = align(tmp->pitch_in_pixels[0], 8);
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if (tmp->tiled) {
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array_mode = tmp->array_mode[0];
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tile_type = tmp->tile_type;
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}
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array_mode = tmp->array_mode[0];
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tile_type = tmp->tile_type;
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/* FIXME properly handle first level != 0 */
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r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0,
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@ -694,7 +692,7 @@ static void evergreen_cb(struct r600_pipe_context *rctx, struct r600_pipe_state
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ntype != 4 && ntype != 5)
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color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
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if (rtex->tiled) {
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if (rtex->array_mode[level] > V_028C70_ARRAY_LINEAR_ALIGNED) {
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tile_type = rtex->tile_type;
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} else /* workaround for linear buffers */
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tile_type = 1;
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@ -59,7 +59,6 @@ struct r600_resource_texture {
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unsigned array_mode[PIPE_MAX_TEXTURE_LEVELS];
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unsigned pitch_override;
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unsigned size;
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unsigned tiled;
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unsigned tile_type;
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unsigned depth;
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unsigned dirty_db;
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@ -67,6 +66,8 @@ struct r600_resource_texture {
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boolean is_flushing_texture;
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};
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#define R600_TEX_IS_TILED(tex, level) ((tex)->array_mode[level] != V_038000_ARRAY_LINEAR_GENERAL && (tex)->array_mode[level] != V_038000_ARRAY_LINEAR_ALIGNED)
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#define R600_BUFFER_MAGIC 0xabcd1600
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/* XXX this could be removed */
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@ -438,10 +438,8 @@ static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *c
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bo[0] = rbuffer->bo;
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bo[1] = rbuffer->bo;
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pitch = align(tmp->pitch_in_pixels[0], 8);
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if (tmp->tiled) {
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array_mode = tmp->array_mode[0];
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tile_type = tmp->tile_type;
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}
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array_mode = tmp->array_mode[0];
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tile_type = tmp->tile_type;
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/* FIXME properly handle first level != 0 */
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r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0,
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@ -388,8 +388,6 @@ r600_texture_create_object(struct pipe_screen *screen,
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if (util_format_is_depth_or_stencil(base->format) && permit_hardware_blit(screen, base))
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rtex->depth = 1;
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if (array_mode)
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rtex->tiled = 1;
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r600_setup_miptree(screen, rtex, array_mode);
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resource->size = rtex->size;
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@ -557,7 +555,7 @@ struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
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* the CPU is much happier reading out of cached system memory
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* than uncached VRAM.
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*/
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if (rtex->tiled)
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if (R600_TEX_IS_TILED(rtex, level))
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use_staging_texture = TRUE;
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if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024)
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