r600g: correct texture memory size for Z32F_S8X24 on evergreen
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@ -232,7 +232,8 @@ static void r600_texture_set_array_mode(struct pipe_screen *screen,
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}
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}
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static int r600_init_surface(struct radeon_surface *surface,
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static int r600_init_surface(struct r600_screen *rscreen,
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struct radeon_surface *surface,
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const struct pipe_resource *ptex,
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unsigned array_mode,
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bool is_transfer, bool is_flushed_depth)
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@ -252,11 +253,19 @@ static int r600_init_surface(struct radeon_surface *surface,
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surface->blk_d = 1;
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surface->array_size = 1;
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surface->last_level = ptex->last_level;
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surface->bpe = util_format_get_blocksize(ptex->format);
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/* align byte per element on dword */
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if (surface->bpe == 3) {
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surface->bpe = 4;
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if (rscreen->chip_class >= EVERGREEN &&
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!is_transfer && !is_flushed_depth &&
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ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
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surface->bpe = 4; /* stencil is allocated separately on evergreen */
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} else {
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surface->bpe = util_format_get_blocksize(ptex->format);
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/* align byte per element on dword */
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if (surface->bpe == 3) {
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surface->bpe = 4;
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}
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}
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surface->nsamples = 1;
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surface->flags = 0;
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switch (array_mode) {
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@ -647,7 +656,7 @@ struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
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}
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}
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r = r600_init_surface(&surface, templ, array_mode,
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r = r600_init_surface(rscreen, &surface, templ, array_mode,
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templ->flags & R600_RESOURCE_FLAG_TRANSFER,
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templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
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if (r) {
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@ -730,7 +739,7 @@ struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
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else
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array_mode = 0;
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r = r600_init_surface(&surface, templ, array_mode, false, false);
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r = r600_init_surface(rscreen, &surface, templ, array_mode, false, false);
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if (r) {
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return NULL;
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}
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