radv: fix wide points/lines by configuring the guardband correctly
Fixes all remaining wide points/lines failures with Zink. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6121 Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17392>
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@ -1344,7 +1344,8 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
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cmd_buffer->scratch_waves_wanted = MAX2(cmd_buffer->scratch_waves_wanted, pipeline->base.max_waves);
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if (!cmd_buffer->state.emitted_graphics_pipeline ||
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cmd_buffer->state.emitted_graphics_pipeline->can_use_guardband != pipeline->can_use_guardband)
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radv_rast_prim_is_points_or_lines(cmd_buffer->state.emitted_graphics_pipeline->rast_prim) != radv_rast_prim_is_points_or_lines(pipeline->rast_prim) ||
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cmd_buffer->state.emitted_graphics_pipeline->line_width != pipeline->line_width)
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cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
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if (!cmd_buffer->state.emitted_graphics_pipeline ||
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@ -1460,11 +1461,24 @@ radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
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static void
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radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
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{
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struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
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uint32_t count = cmd_buffer->state.dynamic.scissor.count;
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unsigned rast_prim;
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if (!(pipeline->dynamic_states & RADV_DYNAMIC_PRIMITIVE_TOPOLOGY) ||
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(pipeline->active_stages & (VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT |
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VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT |
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VK_SHADER_STAGE_GEOMETRY_BIT |
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VK_SHADER_STAGE_MESH_BIT_NV))) {
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/* Ignore dynamic primitive topology for TES/GS/MS stages. */
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rast_prim = pipeline->rast_prim;
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} else {
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rast_prim = si_conv_prim_to_gs_out(cmd_buffer->state.dynamic.primitive_topology);
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}
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si_write_scissors(cmd_buffer->cs, 0, count, cmd_buffer->state.dynamic.scissor.scissors,
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cmd_buffer->state.dynamic.viewport.viewports,
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cmd_buffer->state.emitted_graphics_pipeline->can_use_guardband);
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cmd_buffer->state.dynamic.viewport.viewports, rast_prim,
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cmd_buffer->state.dynamic.line_width);
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cmd_buffer->state.context_roll_without_scissor_emitted = false;
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}
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@ -5345,6 +5359,9 @@ radv_CmdSetLineWidth(VkCommandBuffer commandBuffer, float lineWidth)
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{
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RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
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if (cmd_buffer->state.dynamic.line_width != lineWidth)
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cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
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cmd_buffer->state.dynamic.line_width = lineWidth;
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cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
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}
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@ -5506,11 +5523,15 @@ radv_CmdSetPrimitiveTopology(VkCommandBuffer commandBuffer, VkPrimitiveTopology
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RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
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struct radv_cmd_state *state = &cmd_buffer->state;
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unsigned primitive_topology = si_translate_prim(primitiveTopology);
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bool old_is_linestrip = (state->dynamic.primitive_topology == V_008958_DI_PT_LINESTRIP);
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bool new_is_linestrip = (primitive_topology == V_008958_DI_PT_LINESTRIP);
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if (old_is_linestrip != new_is_linestrip)
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if ((state->dynamic.primitive_topology == V_008958_DI_PT_LINESTRIP) !=
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(primitive_topology == V_008958_DI_PT_LINESTRIP))
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state->dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE;
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if (radv_prim_is_points_or_lines(state->dynamic.primitive_topology) !=
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radv_prim_is_points_or_lines(primitive_topology))
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state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
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state->dynamic.primitive_topology = primitive_topology;
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state->dirty |= RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY;
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@ -1208,28 +1208,6 @@ gfx103_pipeline_init_vrs_state(struct radv_graphics_pipeline *pipeline,
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}
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}
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static bool
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radv_prim_can_use_guardband(uint32_t topology)
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{
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switch (topology) {
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case V_008958_DI_PT_POINTLIST:
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case V_008958_DI_PT_LINELIST:
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case V_008958_DI_PT_LINESTRIP:
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case V_008958_DI_PT_LINELIST_ADJ:
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case V_008958_DI_PT_LINESTRIP_ADJ:
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return false;
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case V_008958_DI_PT_TRILIST:
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case V_008958_DI_PT_TRISTRIP:
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case V_008958_DI_PT_TRIFAN:
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case V_008958_DI_PT_TRILIST_ADJ:
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case V_008958_DI_PT_TRISTRIP_ADJ:
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case V_008958_DI_PT_PATCH:
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return true;
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default:
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unreachable("unhandled primitive type");
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}
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}
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static uint32_t
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si_conv_tess_prim_to_gs_out(enum tess_primitive_mode prim)
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{
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@ -1972,20 +1950,6 @@ static void
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radv_pipeline_init_input_assembly_state(struct radv_graphics_pipeline *pipeline,
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const struct radv_graphics_pipeline_info *info)
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{
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struct radv_shader *tes = pipeline->base.shaders[MESA_SHADER_TESS_EVAL];
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struct radv_shader *gs = pipeline->base.shaders[MESA_SHADER_GEOMETRY];
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pipeline->can_use_guardband = radv_prim_can_use_guardband(info->ia.primitive_topology);
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if (radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY)) {
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if (si_conv_gl_prim_to_gs_out(gs->info.gs.output_prim) == V_028A6C_TRISTRIP)
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pipeline->can_use_guardband = true;
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} else if (radv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_CTRL)) {
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if (!tes->info.tes.point_mode &&
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tes->info.tes._primitive_mode != TESS_PRIMITIVE_ISOLINES)
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pipeline->can_use_guardband = true;
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}
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pipeline->ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline);
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}
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@ -6893,11 +6857,11 @@ radv_pipeline_init_extra(struct radv_graphics_pipeline *pipeline,
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struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
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dynamic->primitive_topology = V_008958_DI_PT_RECTLIST;
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pipeline->can_use_guardband = true;
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*vgt_gs_out_prim_type = V_028A6C_TRISTRIP;
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if (radv_pipeline_has_ngg(pipeline))
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*vgt_gs_out_prim_type = V_028A6C_RECTLIST;
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pipeline->rast_prim = *vgt_gs_out_prim_type;
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}
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if (radv_pipeline_has_ds_attachments(&info->ri)) {
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@ -7033,6 +6997,11 @@ radv_graphics_pipeline_init(struct radv_graphics_pipeline *pipeline, struct radv
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pipeline->force_vrs_per_vertex =
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pipeline->base.shaders[pipeline->last_vgt_api_stage]->info.force_vrs_per_vertex;
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pipeline->uses_user_sample_locations = info.ms.sample_locs_enable;
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pipeline->rast_prim = vgt_gs_out_prim_type;
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if (!(pipeline->dynamic_states & RADV_DYNAMIC_LINE_WIDTH)) {
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pipeline->line_width = info.rs.line_width;
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}
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pipeline->base.push_constant_size = pipeline_layout->push_constant_size;
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pipeline->base.dynamic_offset_count = pipeline_layout->dynamic_offset_count;
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@ -1636,7 +1636,8 @@ void si_emit_compute(struct radv_device *device, struct radeon_cmdbuf *cs);
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void cik_create_gfx_config(struct radv_device *device);
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void si_write_scissors(struct radeon_cmdbuf *cs, int first, int count, const VkRect2D *scissors,
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const VkViewport *viewports, bool can_use_guardband);
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const VkViewport *viewports, unsigned rast_prim, float line_width);
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uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer, bool instanced_draw,
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bool indirect_draw, bool count_from_stream_output,
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uint32_t draw_vertex_count, unsigned topology,
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@ -2121,7 +2122,6 @@ struct radv_graphics_pipeline {
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bool disable_out_of_order_rast_for_occlusion;
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bool uses_drawid;
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bool uses_baseinstance;
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bool can_use_guardband;
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bool uses_dynamic_stride;
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bool uses_conservative_overestimate;
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bool negative_one_to_one;
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@ -2138,6 +2138,9 @@ struct radv_graphics_pipeline {
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/* Not NULL if graphics pipeline uses streamout. */
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struct radv_shader *streamout_shader;
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unsigned rast_prim;
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float line_width;
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};
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struct radv_compute_pipeline {
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@ -3041,6 +3044,36 @@ si_translate_prim(unsigned topology)
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}
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}
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static inline bool
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radv_prim_is_points_or_lines(unsigned topology)
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{
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switch (topology) {
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case V_008958_DI_PT_POINTLIST:
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case V_008958_DI_PT_LINELIST:
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case V_008958_DI_PT_LINESTRIP:
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case V_008958_DI_PT_LINELIST_ADJ:
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case V_008958_DI_PT_LINESTRIP_ADJ:
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return true;
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default:
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return false;
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}
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}
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static inline bool
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radv_rast_prim_is_points_or_lines(unsigned rast_prim)
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{
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switch (rast_prim) {
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case V_028A6C_POINTLIST:
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case V_028A6C_LINESTRIP:
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return true;
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case V_028A6C_TRISTRIP:
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case V_028A6C_RECTLIST:
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return false;
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default:
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unreachable("invalid rast prim");
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}
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}
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static inline uint32_t
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si_translate_stencil_op(enum VkStencilOp op)
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{
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@ -715,10 +715,11 @@ si_intersect_scissor(const VkRect2D *a, const VkRect2D *b)
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void
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si_write_scissors(struct radeon_cmdbuf *cs, int first, int count, const VkRect2D *scissors,
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const VkViewport *viewports, bool can_use_guardband)
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const VkViewport *viewports, unsigned rast_prim, float line_width)
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{
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int i;
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float scale[3], translate[3], guardband_x = INFINITY, guardband_y = INFINITY;
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float discard_x = 1.0f, discard_y = 1.0f;
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const float max_range = 32767.0f;
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if (!count)
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return;
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@ -744,17 +745,33 @@ si_write_scissors(struct radeon_cmdbuf *cs, int first, int count, const VkRect2D
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S_028250_WINDOW_OFFSET_DISABLE(1));
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radeon_emit(cs, S_028254_BR_X(scissor.offset.x + scissor.extent.width) |
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S_028254_BR_Y(scissor.offset.y + scissor.extent.height));
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}
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if (!can_use_guardband) {
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guardband_x = 1.0;
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guardband_y = 1.0;
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if (radv_rast_prim_is_points_or_lines(rast_prim)) {
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/* When rendering wide points or lines, we need to be more conservative about when to
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* discard them entirely. */
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float pixels;
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if (rast_prim == V_028A6C_POINTLIST) {
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pixels = 8191.875f;
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} else {
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pixels = line_width;
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}
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/* Add half the point size / line width. */
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discard_x += pixels / (2.0 * scale[0]);
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discard_y += pixels / (2.0 * scale[1]);
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/* Discard primitives that would lie entirely outside the clip region. */
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discard_x = MIN2(discard_x, guardband_x);
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discard_y = MIN2(discard_y, guardband_y);
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}
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}
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radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
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radeon_emit(cs, fui(guardband_y));
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radeon_emit(cs, fui(1.0));
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radeon_emit(cs, fui(discard_y));
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radeon_emit(cs, fui(guardband_x));
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radeon_emit(cs, fui(1.0));
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radeon_emit(cs, fui(discard_x));
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}
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static inline unsigned
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@ -3,30 +3,6 @@ KHR-GL46.sparse_texture_tests.InternalFormatQueries,Fail
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KHR-GL46.sparse_texture_tests.SparseTextureAllocation,Fail
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KHR-GL46.sparse_texture_tests.SparseTextureCommitment,Fail
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dEQP-GLES2.functional.clipping.line.wide_line_clip_viewport_center,Fail
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dEQP-GLES2.functional.clipping.line.wide_line_clip_viewport_corner,Fail
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dEQP-GLES2.functional.clipping.point.wide_point_clip,Fail
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dEQP-GLES2.functional.clipping.point.wide_point_clip_viewport_center,Fail
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dEQP-GLES2.functional.clipping.point.wide_point_clip_viewport_corner,Fail
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dEQP-GLES2.functional.rasterization.primitives.line_loop_wide,Fail
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dEQP-GLES2.functional.rasterization.primitives.line_strip_wide,Fail
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dEQP-GLES31.functional.primitive_bounding_box.wide_points.global_state.vertex_tessellation_fragment.default_framebuffer_bbox_equal,Fail
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dEQP-GLES31.functional.primitive_bounding_box.wide_points.global_state.vertex_tessellation_fragment.default_framebuffer_bbox_larger,Fail
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dEQP-GLES31.functional.primitive_bounding_box.wide_points.global_state.vertex_tessellation_fragment.fbo_bbox_equal,Fail
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dEQP-GLES31.functional.primitive_bounding_box.wide_points.global_state.vertex_tessellation_fragment.fbo_bbox_larger,Fail
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dEQP-GLES31.functional.primitive_bounding_box.wide_points.tessellation_set_per_draw.vertex_tessellation_fragment.default_framebuffer_bbox_equal,Fail
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dEQP-GLES31.functional.primitive_bounding_box.wide_points.tessellation_set_per_draw.vertex_tessellation_fragment.default_framebuffer_bbox_larger,Fail
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dEQP-GLES31.functional.primitive_bounding_box.wide_points.tessellation_set_per_draw.vertex_tessellation_fragment.fbo_bbox_equal,Fail
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dEQP-GLES31.functional.primitive_bounding_box.wide_points.tessellation_set_per_draw.vertex_tessellation_fragment.fbo_bbox_larger,Fail
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dEQP-GLES31.functional.primitive_bounding_box.wide_points.tessellation_set_per_primitive.vertex_tessellation_fragment.default_framebuffer,Fail
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dEQP-GLES31.functional.primitive_bounding_box.wide_points.tessellation_set_per_primitive.vertex_tessellation_fragment.fbo,Fail
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dEQP-GLES3.functional.clipping.line.wide_line_clip_viewport_center,Fail
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dEQP-GLES3.functional.clipping.line.wide_line_clip_viewport_corner,Fail
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dEQP-GLES3.functional.clipping.point.wide_point_clip,Fail
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dEQP-GLES3.functional.clipping.point.wide_point_clip_viewport_center,Fail
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dEQP-GLES3.functional.clipping.point.wide_point_clip_viewport_corner,Fail
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dEQP-GLES3.functional.rasterization.primitives.line_loop_wide,Fail
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dEQP-GLES3.functional.rasterization.primitives.line_strip_wide,Fail
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dEQP-GLES3.functional.shaders.texture_functions.textureprojlodoffset.sampler2dshadow_vertex,Fail
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dEQP-GLES3.functional.shaders.texture_functions.textureprojoffset.sampler2dshadow_vertex,Fail
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