pan/midgard: Break mir_spill_register into its function
No functional changes, just breaks out a megamonster function and fixes the indentation. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
This commit is contained in:
Alyssa Rosenzweig
parent
d4bcca19da
commit
e94239b9a4
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@ -732,6 +732,142 @@ v_load_store_scratch(
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return ins;
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}
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/* If register allocation fails, find the best spill node and spill it to fix
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* whatever the issue was. This spill node could be a work register (spilling
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* to thread local storage), but it could also simply be a special register
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* that needs to spill to become a work register. */
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static void mir_spill_register(
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compiler_context *ctx,
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struct ra_graph *g,
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unsigned *spill_count)
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{
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unsigned spill_index = ctx->temp_count;
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/* Our first step is to calculate spill cost to figure out the best
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* spill node. All nodes are equal in spill cost, but we can't spill
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* nodes written to from an unspill */
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for (unsigned i = 0; i < ctx->temp_count; ++i) {
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ra_set_node_spill_cost(g, i, 1.0);
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}
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mir_foreach_instr_global(ctx, ins) {
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if (ins->type != TAG_LOAD_STORE_4) continue;
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if (ins->load_store.op != midgard_op_ld_int4) continue;
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if (ins->load_store.arg_1 != 0xEA) continue;
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if (ins->load_store.arg_2 != 0x1E) continue;
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ra_set_node_spill_cost(g, ins->ssa_args.dest, -1.0);
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}
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int spill_node = ra_get_best_spill_node(g);
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if (spill_node < 0) {
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mir_print_shader(ctx);
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assert(0);
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}
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/* We have a spill node, so check the class. Work registers
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* legitimately spill to TLS, but special registers just spill to work
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* registers */
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unsigned class = ra_get_node_class(g, spill_node);
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bool is_special = (class >> 2) != REG_CLASS_WORK;
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bool is_special_w = (class >> 2) == REG_CLASS_TEXW;
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/* Allocate TLS slot (maybe) */
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unsigned spill_slot = !is_special ? (*spill_count)++ : 0;
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midgard_instruction *spill_move = NULL;
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/* For TLS, replace all stores to the spilled node. For
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* special reads, just keep as-is; the class will be demoted
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* implicitly. For special writes, spill to a work register */
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if (!is_special || is_special_w) {
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mir_foreach_instr_global_safe(ctx, ins) {
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if (ins->ssa_args.dest != spill_node) continue;
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midgard_instruction st;
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if (is_special_w) {
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spill_slot = spill_index++;
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st = v_mov(spill_node, blank_alu_src, spill_slot);
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} else {
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ins->ssa_args.dest = SSA_FIXED_REGISTER(26);
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st = v_load_store_scratch(ins->ssa_args.dest, spill_slot, true, ins->mask);
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}
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spill_move = mir_insert_instruction_before(mir_next_op(ins), st);
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if (!is_special)
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ctx->spills++;
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}
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}
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/* Insert a load from TLS before the first consecutive
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* use of the node, rewriting to use spilled indices to
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* break up the live range. Or, for special, insert a
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* move. Ironically the latter *increases* register
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* pressure, but the two uses of the spilling mechanism
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* are somewhat orthogonal. (special spilling is to use
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* work registers to back special registers; TLS
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* spilling is to use memory to back work registers) */
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mir_foreach_block(ctx, block) {
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bool consecutive_skip = false;
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unsigned consecutive_index = 0;
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mir_foreach_instr_in_block(block, ins) {
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/* We can't rewrite the move used to spill in the first place */
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if (ins == spill_move) continue;
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if (!mir_has_arg(ins, spill_node)) {
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consecutive_skip = false;
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continue;
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}
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if (consecutive_skip) {
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/* Rewrite */
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mir_rewrite_index_src_single(ins, spill_node, consecutive_index);
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continue;
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}
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if (!is_special_w) {
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consecutive_index = ++spill_index;
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midgard_instruction *before = ins;
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/* For a csel, go back one more not to break up the bundle */
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if (ins->type == TAG_ALU_4 && OP_IS_CSEL(ins->alu.op))
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before = mir_prev_op(before);
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midgard_instruction st;
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if (is_special) {
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/* Move */
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st = v_mov(spill_node, blank_alu_src, consecutive_index);
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} else {
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/* TLS load */
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st = v_load_store_scratch(consecutive_index, spill_slot, false, 0xF);
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}
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mir_insert_instruction_before(before, st);
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// consecutive_skip = true;
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} else {
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/* Special writes already have their move spilled in */
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consecutive_index = spill_slot;
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}
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/* Rewrite to use */
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mir_rewrite_index_src_single(ins, spill_node, consecutive_index);
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if (!is_special)
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ctx->fills++;
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}
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}
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}
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void
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schedule_program(compiler_context *ctx)
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{
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@ -759,132 +895,8 @@ schedule_program(compiler_context *ctx)
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}
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do {
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/* If we spill, find the best spill node and spill it */
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unsigned spill_index = ctx->temp_count;
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if (g && spilled) {
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/* All nodes are equal in spill cost, but we can't
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* spill nodes written to from an unspill */
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for (unsigned i = 0; i < ctx->temp_count; ++i) {
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ra_set_node_spill_cost(g, i, 1.0);
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}
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mir_foreach_instr_global(ctx, ins) {
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if (ins->type != TAG_LOAD_STORE_4) continue;
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if (ins->load_store.op != midgard_op_ld_int4) continue;
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if (ins->load_store.arg_1 != 0xEA) continue;
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if (ins->load_store.arg_2 != 0x1E) continue;
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ra_set_node_spill_cost(g, ins->ssa_args.dest, -1.0);
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}
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int spill_node = ra_get_best_spill_node(g);
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if (spill_node < 0) {
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mir_print_shader(ctx);
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assert(0);
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}
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/* Check the class. Work registers legitimately spill
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* to TLS, but special registers just spill to work
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* registers */
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unsigned class = ra_get_node_class(g, spill_node);
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bool is_special = (class >> 2) != REG_CLASS_WORK;
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bool is_special_w = (class >> 2) == REG_CLASS_TEXW;
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/* Allocate TLS slot (maybe) */
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unsigned spill_slot = !is_special ? spill_count++ : 0;
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midgard_instruction *spill_move = NULL;
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/* For TLS, replace all stores to the spilled node. For
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* special reads, just keep as-is; the class will be demoted
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* implicitly. For special writes, spill to a work register */
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if (!is_special || is_special_w) {
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mir_foreach_instr_global_safe(ctx, ins) {
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if (ins->ssa_args.dest != spill_node) continue;
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midgard_instruction st;
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if (is_special_w) {
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spill_slot = spill_index++;
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st = v_mov(spill_node, blank_alu_src, spill_slot);
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} else {
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ins->ssa_args.dest = SSA_FIXED_REGISTER(26);
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st = v_load_store_scratch(ins->ssa_args.dest, spill_slot, true, ins->mask);
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}
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spill_move = mir_insert_instruction_before(mir_next_op(ins), st);
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if (!is_special)
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ctx->spills++;
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}
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}
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/* Insert a load from TLS before the first consecutive
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* use of the node, rewriting to use spilled indices to
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* break up the live range. Or, for special, insert a
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* move. Ironically the latter *increases* register
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* pressure, but the two uses of the spilling mechanism
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* are somewhat orthogonal. (special spilling is to use
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* work registers to back special registers; TLS
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* spilling is to use memory to back work registers) */
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mir_foreach_block(ctx, block) {
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bool consecutive_skip = false;
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unsigned consecutive_index = 0;
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mir_foreach_instr_in_block(block, ins) {
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/* We can't rewrite the move used to spill in the first place */
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if (ins == spill_move) continue;
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if (!mir_has_arg(ins, spill_node)) {
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consecutive_skip = false;
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continue;
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}
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if (consecutive_skip) {
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/* Rewrite */
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mir_rewrite_index_src_single(ins, spill_node, consecutive_index);
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continue;
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}
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if (!is_special_w) {
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consecutive_index = ++spill_index;
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midgard_instruction *before = ins;
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/* For a csel, go back one more not to break up the bundle */
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if (ins->type == TAG_ALU_4 && OP_IS_CSEL(ins->alu.op))
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before = mir_prev_op(before);
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midgard_instruction st;
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if (is_special) {
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/* Move */
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st = v_mov(spill_node, blank_alu_src, consecutive_index);
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} else {
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/* TLS load */
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st = v_load_store_scratch(consecutive_index, spill_slot, false, 0xF);
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}
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mir_insert_instruction_before(before, st);
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// consecutive_skip = true;
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} else {
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/* Special writes already have their move spilled in */
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consecutive_index = spill_slot;
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}
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/* Rewrite to use */
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mir_rewrite_index_src_single(ins, spill_node, consecutive_index);
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if (!is_special)
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ctx->fills++;
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}
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}
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}
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if (spilled)
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mir_spill_register(ctx, g, &spill_count);
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mir_squeeze_index(ctx);
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