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i965: Extract tiling from fast clear decision 

There are several constraints when determining if one can fast clear a surface.
Some of these are alignment, pixel density, tiling formats, and others that vary
by generation. The helper function which exists today does a suitable job,
however it conflates "BO properties" with "Miptree properties" when using
tiling. I consider the former to be attributes of the physical surface, things
which are determined through BO allocation, and the latter being attributes
which are derived from the API, and having nothing to do with the underlying
surface.

Determining tiling properties and creating miptrees are related operations
(when we allocate a BO for a miptree) with some disjoint constraints. By
extracting the decisions into two distinct choices (tiling vs. miptree
properties), we gain flexibility throughout the code to make determinations
about when we can or cannot fast clear strictly on the miptree.

To signify this change, I've also renamed the function to indicate it is a
distinction made on the miptree. I am torn as to whether or not it was a good
idea to remove "non_msrt" since it's a really nice thing for grep.

v2:
Reword some comments (Chad)
intel_is_non_msrt_mcs_tile_supported->intel_tiling_supports_non_msrt_mcs (Chad)
Make full if ladder for gens in above function (Chad)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Cc: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
This commit is contained in:
Ben Widawsky 2015-05-21 22:47:37 -07:00
parent b91a110d5c
commit e92fbdcf9c
2 changed files with 30 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
src/mesa/drivers/dri/i965/intel_mipmap_tree.c
View File

@ -158,15 +158,32 @@ intel_get_non_msrt_mcs_alignment(struct brw_context *brw,
}
}
bool
intel_tiling_supports_non_msrt_mcs(struct brw_context *brw, unsigned tiling)
{
/* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
* Target(s)", beneath the "Fast Color Clear" bullet (p326):
*
* - Support is limited to tiled render targets.
*
* Gen9 changes the restriction to Y-tile only.
*/
if (brw->gen >= 9)
return tiling == I915_TILING_Y;
else if (brw->gen >= 7)
return tiling != I915_TILING_NONE;
else
return false;
}
/**
* For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
* can be used.
* can be used. This doesn't (and should not) inspect any of the properties of
* the miptree's BO.
*
* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
* beneath the "Fast Color Clear" bullet (p326):
*
* - Support is limited to tiled render targets.
* - Support is for non-mip-mapped and non-array surface types only.
*
* And then later, on p327:
@ -175,8 +192,8 @@ intel_get_non_msrt_mcs_alignment(struct brw_context *brw,
* 64bpp, and 128bpp.
*/
bool
intel_is_non_msrt_mcs_buffer_supported(struct brw_context *brw,
struct intel_mipmap_tree *mt)
intel_miptree_is_fast_clear_capable(struct brw_context *brw,
struct intel_mipmap_tree *mt)
{
/* MCS support does not exist prior to Gen7 */
if (brw->gen < 7)
@ -193,11 +210,6 @@ intel_is_non_msrt_mcs_buffer_supported(struct brw_context *brw,
return false;
}
if (brw->gen >= 9 && mt->tiling != I915_TILING_Y)
return false;
if (mt->tiling != I915_TILING_X &&
mt->tiling != I915_TILING_Y)
return false;
if (mt->cpp != 4 && mt->cpp != 8 && mt->cpp != 16)
return false;
if (mt->first_level != 0 || mt->last_level != 0) {
@ -625,7 +637,8 @@ intel_miptree_create(struct brw_context *brw,
* Allocation of the MCS miptree will be deferred until the first fast
* clear actually occurs.
*/
if (intel_is_non_msrt_mcs_buffer_supported(brw, mt))
if (intel_tiling_supports_non_msrt_mcs(brw, mt->tiling) &&
intel_miptree_is_fast_clear_capable(brw, mt))
mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_RESOLVED;
return mt;
@ -731,7 +744,8 @@ intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
* Allocation of the MCS miptree will be deferred until the first fast
* clear actually occurs.
*/
if (intel_is_non_msrt_mcs_buffer_supported(intel, singlesample_mt))
if (intel_tiling_supports_non_msrt_mcs(intel, singlesample_mt->tiling) &&
intel_miptree_is_fast_clear_capable(intel, singlesample_mt))
singlesample_mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_RESOLVED;
if (num_samples == 0) {

10
src/mesa/drivers/dri/i965/intel_mipmap_tree.h
View File

@ -522,15 +522,15 @@ enum intel_miptree_tiling_mode {
INTEL_MIPTREE_TILING_NONE,
};
bool
intel_is_non_msrt_mcs_buffer_supported(struct brw_context *brw,
struct intel_mipmap_tree *mt);
void
intel_get_non_msrt_mcs_alignment(struct brw_context *brw,
struct intel_mipmap_tree *mt,
unsigned *width_px, unsigned *height);
bool
intel_tiling_supports_non_msrt_mcs(struct brw_context *brw, unsigned tiling);
bool
intel_miptree_is_fast_clear_capable(struct brw_context *brw,
struct intel_mipmap_tree *mt);
bool
intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
struct intel_mipmap_tree *mt);