anv/cmd_buffer: Move dirty bits into anv_cmd_*_state
Tested-by: Józef Kucia <joseph.kucia@gmail.com> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Cc: "18.0" <mesa-stable@lists.freedesktop.org>
This commit is contained in:
parent
97f96610c8
commit
e85aaec148
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@ -345,7 +345,7 @@ void anv_CmdBindPipeline(
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switch (pipelineBindPoint) {
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case VK_PIPELINE_BIND_POINT_COMPUTE:
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cmd_buffer->state.compute.base.pipeline = pipeline;
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cmd_buffer->state.compute_dirty |= ANV_CMD_DIRTY_PIPELINE;
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cmd_buffer->state.compute.pipeline_dirty = true;
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cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
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cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
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break;
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@ -353,12 +353,12 @@ void anv_CmdBindPipeline(
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case VK_PIPELINE_BIND_POINT_GRAPHICS:
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cmd_buffer->state.gfx.base.pipeline = pipeline;
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cmd_buffer->state.vb_dirty |= pipeline->vb_used;
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cmd_buffer->state.dirty |= ANV_CMD_DIRTY_PIPELINE;
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cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_PIPELINE;
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cmd_buffer->state.push_constants_dirty |= pipeline->active_stages;
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cmd_buffer->state.descriptors_dirty |= pipeline->active_stages;
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/* Apply the dynamic state from the pipeline */
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cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
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cmd_buffer->state.gfx.dirty |= pipeline->dynamic_state_mask;
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anv_dynamic_state_copy(&cmd_buffer->state.dynamic,
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&pipeline->dynamic_state,
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pipeline->dynamic_state_mask);
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@ -385,7 +385,7 @@ void anv_CmdSetViewport(
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memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
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pViewports, viewportCount * sizeof(*pViewports));
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cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_VIEWPORT;
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cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_VIEWPORT;
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}
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void anv_CmdSetScissor(
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@ -403,7 +403,7 @@ void anv_CmdSetScissor(
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memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
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pScissors, scissorCount * sizeof(*pScissors));
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cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_SCISSOR;
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cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_SCISSOR;
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}
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void anv_CmdSetLineWidth(
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@ -413,7 +413,7 @@ void anv_CmdSetLineWidth(
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ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
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cmd_buffer->state.dynamic.line_width = lineWidth;
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cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
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cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
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}
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void anv_CmdSetDepthBias(
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@ -428,7 +428,7 @@ void anv_CmdSetDepthBias(
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cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
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cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
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cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
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cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
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}
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void anv_CmdSetBlendConstants(
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@ -440,7 +440,7 @@ void anv_CmdSetBlendConstants(
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memcpy(cmd_buffer->state.dynamic.blend_constants,
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blendConstants, sizeof(float) * 4);
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cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
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cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
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}
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void anv_CmdSetDepthBounds(
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@ -453,7 +453,7 @@ void anv_CmdSetDepthBounds(
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cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
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cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
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cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
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cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
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}
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void anv_CmdSetStencilCompareMask(
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@ -468,7 +468,7 @@ void anv_CmdSetStencilCompareMask(
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if (faceMask & VK_STENCIL_FACE_BACK_BIT)
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cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
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cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
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cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
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}
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void anv_CmdSetStencilWriteMask(
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@ -483,7 +483,7 @@ void anv_CmdSetStencilWriteMask(
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if (faceMask & VK_STENCIL_FACE_BACK_BIT)
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cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
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cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
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cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
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}
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void anv_CmdSetStencilReference(
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@ -498,7 +498,7 @@ void anv_CmdSetStencilReference(
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if (faceMask & VK_STENCIL_FACE_BACK_BIT)
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cmd_buffer->state.dynamic.stencil_reference.back = reference;
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cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
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cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
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}
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static void
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@ -1691,6 +1691,8 @@ struct anv_cmd_pipeline_state {
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*/
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struct anv_cmd_graphics_state {
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struct anv_cmd_pipeline_state base;
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anv_cmd_dirty_mask_t dirty;
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};
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/** State tracking for compute pipeline
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@ -1702,6 +1704,8 @@ struct anv_cmd_graphics_state {
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*/
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struct anv_cmd_compute_state {
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struct anv_cmd_pipeline_state base;
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bool pipeline_dirty;
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};
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/** State required while building cmd buffer */
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@ -1714,8 +1718,6 @@ struct anv_cmd_state {
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struct anv_cmd_compute_state compute;
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uint32_t vb_dirty;
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anv_cmd_dirty_mask_t dirty;
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anv_cmd_dirty_mask_t compute_dirty;
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enum anv_pipe_bits pending_pipe_bits;
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uint32_t num_workgroups_offset;
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struct anv_bo *num_workgroups_bo;
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@ -113,7 +113,7 @@ void genX(CmdBindIndexBuffer)(
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ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
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ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
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cmd_buffer->state.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
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cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
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if (GEN_IS_HASWELL)
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cmd_buffer->state.restart_index = restart_index_for_type[indexType];
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cmd_buffer->state.gen7.index_buffer = buffer;
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@ -156,10 +156,10 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
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{
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struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
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if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
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ANV_CMD_DIRTY_RENDER_TARGETS |
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ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH |
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ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
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if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
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ANV_CMD_DIRTY_RENDER_TARGETS |
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ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH |
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ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
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uint32_t sf_dw[GENX(3DSTATE_SF_length)];
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struct GENX(3DSTATE_SF) sf = {
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GENX(3DSTATE_SF_header),
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@ -174,8 +174,8 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
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anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gen7.sf);
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}
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if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
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if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
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struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
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struct anv_state cc_state =
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anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
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@ -197,10 +197,10 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
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}
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}
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if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
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ANV_CMD_DIRTY_RENDER_TARGETS |
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
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if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
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ANV_CMD_DIRTY_RENDER_TARGETS |
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
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uint32_t depth_stencil_dw[GENX(DEPTH_STENCIL_STATE_length)];
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struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
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@ -229,8 +229,8 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
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}
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if (cmd_buffer->state.gen7.index_buffer &&
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cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
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ANV_CMD_DIRTY_INDEX_BUFFER)) {
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cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
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ANV_CMD_DIRTY_INDEX_BUFFER)) {
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struct anv_buffer *buffer = cmd_buffer->state.gen7.index_buffer;
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uint32_t offset = cmd_buffer->state.gen7.index_offset;
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@ -255,7 +255,7 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
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}
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}
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cmd_buffer->state.dirty = 0;
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cmd_buffer->state.gfx.dirty = 0;
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}
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void
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@ -383,8 +383,8 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
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{
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struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
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if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
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ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)) {
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if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
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ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)) {
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uint32_t sf_dw[GENX(3DSTATE_SF_length)];
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struct GENX(3DSTATE_SF) sf = {
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GENX(3DSTATE_SF_header),
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@ -402,8 +402,8 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
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anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gen8.sf);
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}
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if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
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ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)){
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if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
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ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)){
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uint32_t raster_dw[GENX(3DSTATE_RASTER_length)];
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struct GENX(3DSTATE_RASTER) raster = {
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GENX(3DSTATE_RASTER_header),
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@ -422,8 +422,8 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
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* using a big old #if switch here.
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*/
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#if GEN_GEN == 8
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if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
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if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
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struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
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struct anv_state cc_state =
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anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
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@ -447,10 +447,10 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
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}
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}
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if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
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ANV_CMD_DIRTY_RENDER_TARGETS |
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
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if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
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ANV_CMD_DIRTY_RENDER_TARGETS |
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
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uint32_t wm_depth_stencil_dw[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
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struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
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@ -477,7 +477,7 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
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want_depth_pma_fix(cmd_buffer));
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}
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#else
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if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
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if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
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struct anv_state cc_state =
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anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
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GENX(COLOR_CALC_STATE_length) * 4,
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@ -498,11 +498,11 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
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}
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}
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if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
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ANV_CMD_DIRTY_RENDER_TARGETS |
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
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if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
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ANV_CMD_DIRTY_RENDER_TARGETS |
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
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uint32_t dwords[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
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struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
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struct GENX(3DSTATE_WM_DEPTH_STENCIL) wm_depth_stencil = {
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}
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#endif
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if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
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ANV_CMD_DIRTY_INDEX_BUFFER)) {
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if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
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ANV_CMD_DIRTY_INDEX_BUFFER)) {
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF), vf) {
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vf.IndexedDrawCutIndexEnable = pipeline->primitive_restart;
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vf.CutIndex = cmd_buffer->state.restart_index;
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}
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}
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cmd_buffer->state.dirty = 0;
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cmd_buffer->state.gfx.dirty = 0;
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}
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void genX(CmdBindIndexBuffer)(
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ib.BufferSize = buffer->size - offset;
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}
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cmd_buffer->state.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
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cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
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}
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/* Set of stage bits for which are pipelined, i.e. they get queued by the
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@ -219,6 +219,6 @@ genX(blorp_exec)(struct blorp_batch *batch,
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blorp_exec(batch, params);
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cmd_buffer->state.vb_dirty = ~0;
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cmd_buffer->state.dirty = ~0;
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cmd_buffer->state.gfx.dirty = ~0;
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cmd_buffer->state.push_constants_dirty = ~0;
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}
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@ -1002,7 +1002,7 @@ genX(BeginCommandBuffer)(
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}
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}
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cmd_buffer->state.dirty |= ANV_CMD_DIRTY_RENDER_TARGETS;
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cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_RENDER_TARGETS;
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}
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return result;
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@ -2064,7 +2064,7 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
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cmd_buffer->state.vb_dirty &= ~vb_emit;
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if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_PIPELINE) {
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if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_PIPELINE) {
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anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
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/* The exact descriptor layout is pulled from the pipeline, so we need
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@ -2101,7 +2101,7 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
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#endif
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/* Render targets live in the same binding table as fragment descriptors */
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if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_RENDER_TARGETS)
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if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_RENDER_TARGETS)
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cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_FRAGMENT_BIT;
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/* We emit the binding tables and sampler tables first, then emit push
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@ -2127,16 +2127,16 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
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if (dirty)
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cmd_buffer_emit_descriptor_pointers(cmd_buffer, dirty);
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if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_DYNAMIC_VIEWPORT)
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if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_VIEWPORT)
|
||||
gen8_cmd_buffer_emit_viewport(cmd_buffer);
|
||||
|
||||
if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT |
|
||||
if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT |
|
||||
ANV_CMD_DIRTY_PIPELINE)) {
|
||||
gen8_cmd_buffer_emit_depth_viewport(cmd_buffer,
|
||||
pipeline->depth_clamp_enable);
|
||||
}
|
||||
|
||||
if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_DYNAMIC_SCISSOR)
|
||||
if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_SCISSOR)
|
||||
gen7_cmd_buffer_emit_scissor(cmd_buffer);
|
||||
|
||||
genX(cmd_buffer_flush_dynamic_state)(cmd_buffer);
|
||||
|
@ -2541,7 +2541,7 @@ genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer)
|
|||
|
||||
genX(flush_pipeline_select_gpgpu)(cmd_buffer);
|
||||
|
||||
if (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE) {
|
||||
if (cmd_buffer->state.compute.pipeline_dirty) {
|
||||
/* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
|
||||
*
|
||||
* "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
|
||||
|
@ -2557,7 +2557,7 @@ genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer)
|
|||
}
|
||||
|
||||
if ((cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_COMPUTE_BIT) ||
|
||||
(cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)) {
|
||||
cmd_buffer->state.compute.pipeline_dirty) {
|
||||
/* FIXME: figure out descriptors for gen7 */
|
||||
result = flush_compute_descriptor_set(cmd_buffer);
|
||||
if (result != VK_SUCCESS)
|
||||
|
@ -2578,7 +2578,7 @@ genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer)
|
|||
}
|
||||
}
|
||||
|
||||
cmd_buffer->state.compute_dirty = 0;
|
||||
cmd_buffer->state.compute.pipeline_dirty = false;
|
||||
|
||||
genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
|
||||
}
|
||||
|
@ -3140,7 +3140,7 @@ genX(cmd_buffer_set_subpass)(struct anv_cmd_buffer *cmd_buffer,
|
|||
{
|
||||
cmd_buffer->state.subpass = subpass;
|
||||
|
||||
cmd_buffer->state.dirty |= ANV_CMD_DIRTY_RENDER_TARGETS;
|
||||
cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_RENDER_TARGETS;
|
||||
|
||||
/* Our implementation of VK_KHR_multiview uses instancing to draw the
|
||||
* different views. If the client asks for instancing, we need to use the
|
||||
|
|
|
@ -272,5 +272,5 @@ genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer,
|
|||
prim.BaseVertexLocation = 0;
|
||||
}
|
||||
|
||||
cmd_buffer->state.dirty |= ANV_CMD_DIRTY_PIPELINE;
|
||||
cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_PIPELINE;
|
||||
}
|
||||
|
|
Loading…
Reference in New Issue