pan/midgard: Add a dummy source for loads
We want symmetry between loads and stores, so we add a dummy source. So we get, e.g. st_int4 _, val, arg_1, arg_2 ld_int4 dest, _, arg_1, arg_2 Semantically, this dummy source represents the data itself, as if the load is simply a move. That means it has a swizzle that acts as a source. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
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@ -1125,7 +1125,7 @@ emit_ubo_read(
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ins.mask = mir_mask_for_intr(instr, true);
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ins.mask = mir_mask_for_intr(instr, true);
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if (indirect_offset) {
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if (indirect_offset) {
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ins.src[1] = nir_src_index(ctx, indirect_offset);
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ins.src[2] = nir_src_index(ctx, indirect_offset);
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ins.load_store.arg_2 = 0x80;
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ins.load_store.arg_2 = 0x80;
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} else {
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} else {
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ins.load_store.arg_2 = 0x1E;
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ins.load_store.arg_2 = 0x1E;
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@ -1163,16 +1163,9 @@ emit_ssbo_access(
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unsigned addr = make_compiler_temp(ctx);
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unsigned addr = make_compiler_temp(ctx);
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emit_sysval_read(ctx, instr, addr, 2);
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emit_sysval_read(ctx, instr, addr, 2);
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/* The source array is a bit of a leaky abstraction for SSBOs.
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/* The source array:
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* Nevertheless, for loads:
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*
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*
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* src[0] = arg_1
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* src[0] = store ? value : unused
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* src[1] = arg_2
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* src[2] = unused
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*
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* Whereas for stores:
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*
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* src[0] = value
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* src[1] = arg_1
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* src[1] = arg_1
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* src[2] = arg_2
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* src[2] = arg_2
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*
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*
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@ -1180,7 +1173,7 @@ emit_ssbo_access(
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* arg_2 = the offset.
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* arg_2 = the offset.
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*/
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*/
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ins.src[is_read ? 0 : 1] = addr;
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ins.src[1] = addr;
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/* TODO: What is this? It looks superficially like a shift << 5, but
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/* TODO: What is this? It looks superficially like a shift << 5, but
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* arg_1 doesn't take a shift Should it be E0 or A0? We also need the
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* arg_1 doesn't take a shift Should it be E0 or A0? We also need the
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@ -1188,7 +1181,7 @@ emit_ssbo_access(
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if (indirect_offset) {
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if (indirect_offset) {
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ins.load_store.arg_1 |= 0xE0;
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ins.load_store.arg_1 |= 0xE0;
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ins.src[is_read ? 1 : 2] = nir_src_index(ctx, indirect_offset);
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ins.src[2] = nir_src_index(ctx, indirect_offset);
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} else {
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} else {
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ins.load_store.arg_2 = 0x7E;
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ins.load_store.arg_2 = 0x7E;
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}
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}
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@ -1229,7 +1222,7 @@ emit_varying_read(
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ins.load_store.varying_parameters = u;
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ins.load_store.varying_parameters = u;
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if (indirect_offset)
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if (indirect_offset)
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ins.src[1] = nir_src_index(ctx, indirect_offset);
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ins.src[2] = nir_src_index(ctx, indirect_offset);
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else
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else
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ins.load_store.arg_2 = 0x1E;
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ins.load_store.arg_2 = 0x1E;
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@ -1715,7 +1708,7 @@ emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
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unsigned temp = make_compiler_temp(ctx);
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unsigned temp = make_compiler_temp(ctx);
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midgard_instruction ld = m_ld_cubemap_coords(temp, 0);
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midgard_instruction ld = m_ld_cubemap_coords(temp, 0);
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ld.src[0] = index;
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ld.src[1] = index;
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ld.mask = 0x3; /* xy */
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ld.mask = 0x3; /* xy */
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ld.load_store.arg_1 = 0x20;
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ld.load_store.arg_1 = 0x20;
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ld.load_store.swizzle = alu_src.swizzle;
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ld.load_store.swizzle = alu_src.swizzle;
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@ -744,21 +744,18 @@ install_registers_instr(
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/* We also follow up by actual arguments */
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/* We also follow up by actual arguments */
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unsigned src2_idx = encodes_src ? 1 : 0;
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unsigned src2 = ins->src[1];
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unsigned src3_idx = encodes_src ? 2 : 1;
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unsigned src3 = ins->src[2];
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unsigned src2 = ins->src[src2_idx];
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unsigned src3 = ins->src[src3_idx];
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if (src2 != ~0) {
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if (src2 != ~0) {
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struct phys_reg src = index_to_reg(ctx, g, src2, mir_srcsize(ins, src2_idx));
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struct phys_reg src = index_to_reg(ctx, g, src2, mir_srcsize(ins, 1));
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unsigned component = src.offset / src.size;
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unsigned component = src.offset / src.size;
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assert(component * src.size == src.offset);
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assert(component * src.size == src.offset);
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ins->load_store.arg_1 |= midgard_ldst_reg(src.reg, component);
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ins->load_store.arg_1 |= midgard_ldst_reg(src.reg, component);
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}
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}
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if (src3 != ~0) {
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if (src3 != ~0) {
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struct phys_reg src = index_to_reg(ctx, g, src3, mir_srcsize(ins, src3_idx));
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struct phys_reg src = index_to_reg(ctx, g, src3, mir_srcsize(ins, 2));
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unsigned component = src.offset / src.size;
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unsigned component = src.offset / src.size;
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assert(component * src.size == src.offset);
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assert(component * src.size == src.offset);
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ins->load_store.arg_2 |= midgard_ldst_reg(src.reg, component);
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ins->load_store.arg_2 |= midgard_ldst_reg(src.reg, component);
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@ -54,10 +54,6 @@ mir_get_swizzle(midgard_instruction *ins, unsigned idx)
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return (mir_get_alu_src(ins, idx)).swizzle;
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return (mir_get_alu_src(ins, idx)).swizzle;
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} else if (ins->type == TAG_LOAD_STORE_4) {
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} else if (ins->type == TAG_LOAD_STORE_4) {
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/* Main swizzle of a load is on the destination */
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if (!OP_IS_STORE(ins->load_store.op))
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idx++;
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switch (idx) {
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switch (idx) {
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case 0:
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case 0:
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return ins->load_store.swizzle;
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return ins->load_store.swizzle;
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@ -131,10 +127,6 @@ mir_set_swizzle(midgard_instruction *ins, unsigned idx, unsigned new)
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else
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else
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ins->alu.src2 = pack;
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ins->alu.src2 = pack;
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} else if (ins->type == TAG_LOAD_STORE_4) {
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} else if (ins->type == TAG_LOAD_STORE_4) {
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/* Main swizzle of a load is on the destination */
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if (!OP_IS_STORE(ins->load_store.op))
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idx++;
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switch (idx) {
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switch (idx) {
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case 0:
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case 0:
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ins->load_store.swizzle = new;
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ins->load_store.swizzle = new;
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