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radv: check if HTILE is enabled per-level instead of the entire image 

With HTILE mipmaps support, we should check if the base level
currently in use supports compression.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8124>
This commit is contained in:
Samuel Pitoiset 2020-12-15 18:37:48 +01:00
parent 8f1db7401a
commit e7d898a268
2 changed files with 4 additions and 3 deletions
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4
src/amd/vulkan/radv_cmd_buffer.c
View File

@ -2058,7 +2058,7 @@ radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
};
struct radv_image *image = iview->image;
assert(radv_image_has_htile(image));
assert(radv_htile_enabled(image, range.baseMipLevel));
radv_set_ds_clear_metadata(cmd_buffer, iview->image, &range,
ds_clear_value, aspects);
@ -6156,7 +6156,7 @@ static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffe
{
struct radv_device *device = cmd_buffer->device;
if (!radv_image_has_htile(image))
if (!radv_htile_enabled(image, range->baseMipLevel))
return;
if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {

3
src/amd/vulkan/radv_meta_clear.c
View File

@ -699,7 +699,8 @@ static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer,
clear_value.depth != 1.0) ||
((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) && clear_value.stencil != 0)))
return false;
if (iview->base_mip == 0 &&
if (radv_htile_enabled(iview->image, iview->base_mip) &&
iview->base_mip == 0 &&
iview->base_layer == 0 &&
iview->layer_count == iview->image->info.array_size &&
radv_layout_is_htile_compressed(cmd_buffer->device, iview->image, layout, in_render_loop, queue_mask) &&