r600g: don't need 3 bos here.
the code should reloc correctly a single BO 3 times.
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@ -120,12 +120,8 @@ static void r600_cb(struct r600_context *rctx, struct radeon_state *rstate,
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rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
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rbuffer = &rtex->resource;
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rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
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rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
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rstate->bo[2] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
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rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
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rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
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rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
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rstate->nbo = 3;
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rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
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rstate->nbo = 1;
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pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
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slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
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@ -404,8 +404,8 @@ static const struct radeon_register R600_names_CB0[] = {
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{0x000280A0, 0, 0, "CB_COLOR0_INFO"},
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{0x00028060, 0, 0, "CB_COLOR0_SIZE"},
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{0x00028080, 0, 0, "CB_COLOR0_VIEW"},
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{0x000280E0, 1, 1, "CB_COLOR0_FRAG"},
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{0x000280C0, 1, 2, "CB_COLOR0_TILE"},
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{0x000280E0, 1, 0, "CB_COLOR0_FRAG"},
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{0x000280C0, 1, 0, "CB_COLOR0_TILE"},
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{0x00028100, 0, 0, "CB_COLOR0_MASK"},
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};
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