From e77ff11ffe1a52b8e17a847f263746c849db3f11 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 26 Jul 2017 02:34:54 +0100 Subject: [PATCH] radv/ac: port SI TC L1 write corruption fix. This ports 72e46c988 to radv. radeonsi: apply a TC L1 write corruption workaround for SI Fixes: f4e499ec7 (radv: add initial non-conformant radv vulkan driver) Reviewed-by: Bas Nieuwenhuizen Signed-off-by: Dave Airlie --- src/amd/common/ac_nir_to_llvm.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index a427f484b56..d6b450f8ee1 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_nir_to_llvm.c @@ -3400,7 +3400,10 @@ static void visit_image_store(struct nir_to_llvm_context *ctx, char intrinsic_name[64]; const nir_variable *var = instr->variables[0]->var; const struct glsl_type *type = glsl_without_array(var->type); - + LLVMValueRef glc = ctx->i1false; + bool force_glc = ctx->options->chip_class == SI; + if (force_glc) + glc = ctx->i1true; if (ctx->stage == MESA_SHADER_FRAGMENT) ctx->shader_info->fs.writes_memory = true; @@ -3410,7 +3413,7 @@ static void visit_image_store(struct nir_to_llvm_context *ctx, params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]), LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */ params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */ - params[4] = ctx->i1false; /* glc */ + params[4] = glc; /* glc */ params[5] = ctx->i1false; /* slc */ ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt, params, 6, 0); @@ -3418,7 +3421,6 @@ static void visit_image_store(struct nir_to_llvm_context *ctx, bool is_da = glsl_sampler_type_is_array(type) || glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE; LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false; - LLVMValueRef glc = ctx->i1false; LLVMValueRef slc = ctx->i1false; params[0] = to_float(&ctx->ac, get_src(ctx, instr->src[2]));