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pan/midgard: Set r1.w magic 

I'm honestly unsure what this is for, but it's needed on MFBD systems
for unknown reasons, at least when MRT is actually in use and then
sometimes without MRT (it fixes a blend shader issue on T760?)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Visoso <tomeu.vizoso@collabora.com>
This commit is contained in:
Alyssa Rosenzweig 2019-12-03 10:51:38 -05:00 committed by Tomeu Vizoso
parent 3448b2641a
commit e7721d8775
4 changed files with 32 additions and 4 deletions
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1
.gitlab-ci/deqp-panfrost-t760-fails.txt
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@ -29,6 +29,5 @@ dEQP-GLES2.functional.fbo.render.shared_depthbuffer.tex2d_rgba_depth_component16
dEQP-GLES2.functional.fbo.render.shared_depthbuffer.tex2d_rgb_depth_component16 Fail
dEQP-GLES2.functional.fbo.render.shared_depthbuffer.rbo_rgb5_a1_depth_component16 Fail
dEQP-GLES2.functional.fbo.render.shared_depthbuffer.rbo_rgba4_depth_component16 Fail
dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.6 Fail
dEQP-GLES2.functional.shaders.scoping.valid.local_variable_hides_function_parameter_fragment Fail
dEQP-GLES2.functional.shaders.scoping.valid.local_variable_hides_function_parameter_vertex Fail

4
src/panfrost/midgard/midgard_compile.c
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@ -1339,7 +1339,7 @@ emit_fragment_store(compiler_context *ctx, unsigned src, unsigned rt)
emit_explicit_constant(ctx, src, src);
struct midgard_instruction ins =
v_alu_br_compact_cond(midgard_jmp_writeout_op_writeout, TAG_ALU_4, 0, midgard_condition_always);
v_alu_br_compact_cond(midgard_jmp_writeout_op_writeout, TAG_ALU_8, 0, midgard_condition_always);
/* Add dependencies */
ins.src[0] = src;
@ -2216,7 +2216,7 @@ emit_fragment_epilogue(compiler_context *ctx, unsigned rt)
emit_mir_instruction(ctx, rt_move);
}
EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, ~0, midgard_condition_always);
EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_8, -2, midgard_condition_always);
ctx->current_block->epilogue = true;
schedule_barrier(ctx);
}

5
src/panfrost/midgard/midgard_ra.c
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@ -524,7 +524,7 @@ allocate_registers(compiler_context *ctx, bool *spilled)
assert(check_read_class(l->class, ins->type, ins->src[2]));
}
/* Mark writeout to r0, render target to r1.z */
/* Mark writeout to r0, render target to r1.z, unknown to r1.w */
mir_foreach_instr_global(ctx, ins) {
if (!(ins->compact_branch && ins->writeout)) continue;
@ -533,6 +533,9 @@ allocate_registers(compiler_context *ctx, bool *spilled)
if (ins->src[1] < ctx->temp_count)
l->solutions[ins->src[1]] = (16 * 1) + COMPONENT_Z * 4;
if (ins->src[2] < ctx->temp_count)
l->solutions[ins->src[2]] = (16 * 1) + COMPONENT_W * 4;
}
mir_compute_interference(ctx, l);

26
src/panfrost/midgard/midgard_schedule.c
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@ -889,6 +889,32 @@ mir_schedule_alu(
if (!writeout)
mir_choose_alu(&vlut, instructions, worklist, len, &predicate, UNIT_VLUT);
if (writeout) {
midgard_instruction add = v_mov(~0, make_compiler_temp(ctx));
if (!ctx->is_blend) {
add.alu.op = midgard_alu_op_iadd;
add.src[0] = SSA_FIXED_REGISTER(31);
for (unsigned c = 0; c < 16; ++c)
add.swizzle[0][c] = COMPONENT_X;
add.has_inline_constant = true;
add.inline_constant = 0;
} else {
add.src[1] = SSA_FIXED_REGISTER(1);
for (unsigned c = 0; c < 16; ++c)
add.swizzle[1][c] = COMPONENT_W;
}
vadd = mem_dup(&add, sizeof(midgard_instruction));
vadd->unit = UNIT_VADD;
vadd->mask = 0x1;
branch->src[2] = add.dest;
}
mir_choose_alu(&vadd, instructions, worklist, len, &predicate, UNIT_VADD);
mir_update_worklist(worklist, len, instructions, vlut);