From e76956b9e01f95df79f568a7bd70ba40be22285b Mon Sep 17 00:00:00 2001 From: Joshua Ashton Date: Fri, 1 Oct 2021 22:53:43 +0100 Subject: [PATCH] radeonsi: Use common DCC image store check MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We need to keep RADV and RadeonSI on the same page about this due to modifiers. Signed-off-by: Joshua Ashton Reviewed-by: Bas Nieuwenhuizen Reviewed-by: Marek Olšák Part-of: --- src/gallium/drivers/radeonsi/si_descriptors.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index 69d485a462e..f02855743a5 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -369,11 +369,8 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture * The same limitations apply to SDMA compressed stores because * SDMA uses the same DCC codec. */ - S_00A018_WRITE_COMPRESS_ENABLE(!tex->surface.u.gfx9.color.dcc.independent_64B_blocks && - tex->surface.u.gfx9.color.dcc.independent_128B_blocks && - tex->surface.u.gfx9.color.dcc.max_compressed_block_size == - V_028C78_MAX_BLOCK_SIZE_128B && - access & SI_IMAGE_ACCESS_ALLOW_DCC_STORE); + S_00A018_WRITE_COMPRESS_ENABLE(ac_surface_supports_dcc_image_stores(sscreen->info.chip_class, &tex->surface) && + (access & SI_IMAGE_ACCESS_ALLOW_DCC_STORE)); } state[7] = meta_va >> 16;