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aco: move some setup code into helpers 

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6013>
This commit is contained in:
Rhys Perry 2020-01-22 19:57:20 +00:00 committed by Marge Bot
parent 2907faee7a
commit e75946cfef
5 changed files with 146 additions and 103 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
src/amd/compiler/aco_instruction_selection.cpp
View File

@ -11029,16 +11029,6 @@ void select_gs_copy_shader(Program *program, struct nir_shader *gs_shader,
{
isel_context ctx = setup_isel_context(program, 1, &gs_shader, config, args, true);
program->next_fp_mode.preserve_signed_zero_inf_nan32 = false;
program->next_fp_mode.preserve_signed_zero_inf_nan16_64 = false;
program->next_fp_mode.must_flush_denorms32 = false;
program->next_fp_mode.must_flush_denorms16_64 = false;
program->next_fp_mode.care_about_round32 = false;
program->next_fp_mode.care_about_round16_64 = false;
program->next_fp_mode.denorm16_64 = fp_denorm_keep;
program->next_fp_mode.denorm32 = 0;
program->next_fp_mode.round32 = fp_round_ne;
program->next_fp_mode.round16_64 = fp_round_ne;
ctx.block->fp_mode = program->next_fp_mode;
add_startpgm(&ctx);

108
src/amd/compiler/aco_instruction_selection_setup.cpp
View File

@ -1422,26 +1422,26 @@ setup_isel_context(Program* program,
struct radv_shader_args *args,
bool is_gs_copy_shader)
{
program->stage = 0;
Stage stage = 0;
for (unsigned i = 0; i < shader_count; i++) {
switch (shaders[i]->info.stage) {
case MESA_SHADER_VERTEX:
program->stage |= sw_vs;
stage |= sw_vs;
break;
case MESA_SHADER_TESS_CTRL:
program->stage |= sw_tcs;
stage |= sw_tcs;
break;
case MESA_SHADER_TESS_EVAL:
program->stage |= sw_tes;
stage |= sw_tes;
break;
case MESA_SHADER_GEOMETRY:
program->stage |= is_gs_copy_shader ? sw_gs_copy : sw_gs;
stage |= is_gs_copy_shader ? sw_gs_copy : sw_gs;
break;
case MESA_SHADER_FRAGMENT:
program->stage |= sw_fs;
stage |= sw_fs;
break;
case MESA_SHADER_COMPUTE:
program->stage |= sw_cs;
stage |= sw_cs;
break;
default:
unreachable("Shader stage not implemented");
@ -1449,71 +1449,41 @@ setup_isel_context(Program* program,
}
bool gfx9_plus = args->options->chip_class >= GFX9;
bool ngg = args->shader_info->is_ngg && args->options->chip_class >= GFX10;
if (program->stage == sw_vs && args->shader_info->vs.as_es && !ngg)
program->stage |= hw_es;
else if (program->stage == sw_vs && !args->shader_info->vs.as_ls && !ngg)
program->stage |= hw_vs;
else if (program->stage == sw_vs && ngg)
program->stage |= hw_ngg_gs; /* GFX10/NGG: VS without GS uses the HW GS stage */
else if (program->stage == sw_gs)
program->stage |= hw_gs;
else if (program->stage == sw_fs)
program->stage |= hw_fs;
else if (program->stage == sw_cs)
program->stage |= hw_cs;
else if (program->stage == sw_gs_copy)
program->stage |= hw_vs;
else if (program->stage == (sw_vs | sw_gs) && gfx9_plus && !ngg)
program->stage |= hw_gs;
else if (program->stage == sw_vs && args->shader_info->vs.as_ls)
program->stage |= hw_ls; /* GFX6-8: VS is a Local Shader, when tessellation is used */
else if (program->stage == sw_tcs)
program->stage |= hw_hs; /* GFX6-8: TCS is a Hull Shader */
else if (program->stage == (sw_vs | sw_tcs))
program->stage |= hw_hs; /* GFX9-10: VS+TCS merged into a Hull Shader */
else if (program->stage == sw_tes && !args->shader_info->tes.as_es && !ngg)
program->stage |= hw_vs; /* GFX6-9: TES without GS uses the HW VS stage (and GFX10/legacy) */
else if (program->stage == sw_tes && !args->shader_info->tes.as_es && ngg)
program->stage |= hw_ngg_gs; /* GFX10/NGG: TES without GS uses the HW GS stage */
else if (program->stage == sw_tes && args->shader_info->tes.as_es && !ngg)
program->stage |= hw_es; /* GFX6-8: TES is an Export Shader */
else if (program->stage == (sw_tes | sw_gs) && gfx9_plus && !ngg)
program->stage |= hw_gs; /* GFX9: TES+GS merged into a GS (and GFX10/legacy) */
if (stage == sw_vs && args->shader_info->vs.as_es && !ngg)
stage |= hw_es;
else if (stage == sw_vs && !args->shader_info->vs.as_ls && !ngg)
stage |= hw_vs;
else if (stage == sw_vs && ngg)
stage |= hw_ngg_gs; /* GFX10/NGG: VS without GS uses the HW GS stage */
else if (stage == sw_gs)
stage |= hw_gs;
else if (stage == sw_fs)
stage |= hw_fs;
else if (stage == sw_cs)
stage |= hw_cs;
else if (stage == sw_gs_copy)
stage |= hw_vs;
else if (stage == (sw_vs | sw_gs) && gfx9_plus && !ngg)
stage |= hw_gs;
else if (stage == sw_vs && args->shader_info->vs.as_ls)
stage |= hw_ls; /* GFX6-8: VS is a Local Shader, when tessellation is used */
else if (stage == sw_tcs)
stage |= hw_hs; /* GFX6-8: TCS is a Hull Shader */
else if (stage == (sw_vs | sw_tcs))
stage |= hw_hs; /* GFX9-10: VS+TCS merged into a Hull Shader */
else if (stage == sw_tes && !args->shader_info->tes.as_es && !ngg)
stage |= hw_vs; /* GFX6-9: TES without GS uses the HW VS stage (and GFX10/legacy) */
else if (stage == sw_tes && !args->shader_info->tes.as_es && ngg)
stage |= hw_ngg_gs; /* GFX10/NGG: TES without GS uses the HW GS stage */
else if (stage == sw_tes && args->shader_info->tes.as_es && !ngg)
stage |= hw_es; /* GFX6-8: TES is an Export Shader */
else if (stage == (sw_tes | sw_gs) && gfx9_plus && !ngg)
stage |= hw_gs; /* GFX9: TES+GS merged into a GS (and GFX10/legacy) */
else
unreachable("Shader stage not implemented");
program->config = config;
program->info = args->shader_info;
program->chip_class = args->options->chip_class;
program->family = args->options->family;
program->wave_size = args->shader_info->wave_size;
program->lane_mask = program->wave_size == 32 ? s1 : s2;
program->lds_alloc_granule = args->options->chip_class >= GFX7 ? 512 : 256;
program->lds_limit = args->options->chip_class >= GFX7 ? 65536 : 32768;
/* apparently gfx702 also has 16-bank LDS but I can't find a family for that */
program->has_16bank_lds = args->options->family == CHIP_KABINI || args->options->family == CHIP_STONEY;
program->vgpr_limit = 256;
program->vgpr_alloc_granule = 3;
if (args->options->chip_class >= GFX10) {
program->physical_sgprs = 2560; /* doesn't matter as long as it's at least 128 * 20 */
program->sgpr_alloc_granule = 127;
program->sgpr_limit = 106;
program->vgpr_alloc_granule = program->wave_size == 32 ? 7 : 3;
} else if (program->chip_class >= GFX8) {
program->physical_sgprs = 800;
program->sgpr_alloc_granule = 15;
if (args->options->family == CHIP_TONGA || args->options->family == CHIP_ICELAND)
program->sgpr_limit = 94; /* workaround hardware bug */
else
program->sgpr_limit = 102;
} else {
program->physical_sgprs = 512;
program->sgpr_alloc_granule = 7;
program->sgpr_limit = 104;
}
init_program(program, stage, args->shader_info,
args->options->chip_class, args->options->family, config);
isel_context ctx = {};
ctx.program = program;

25
src/amd/compiler/aco_interface.cpp
View File

@ -31,29 +31,6 @@
#include <iostream>
#include <sstream>
namespace aco {
uint64_t debug_flags = 0;
static const struct debug_control aco_debug_options[] = {
{"validateir", DEBUG_VALIDATE},
{"validatera", DEBUG_VALIDATE_RA},
{"perfwarn", DEBUG_PERFWARN},
{NULL, 0}
};
static once_flag init_once_flag = ONCE_FLAG_INIT;
static void init()
{
debug_flags = parse_debug_string(getenv("ACO_DEBUG"), aco_debug_options);
#ifndef NDEBUG
/* enable some flags by default on debug builds */
debug_flags |= aco::DEBUG_VALIDATE;
#endif
}
}
static radv_compiler_statistic_info statistic_infos[] = {
[aco::statistic_hash] = {"Hash", "CRC32 hash of code and constant data"},
[aco::statistic_instructions] = {"Instructions", "Instruction count"},
@ -73,7 +50,7 @@ void aco_compile_shader(unsigned shader_count,
struct radv_shader_binary **binary,
struct radv_shader_args *args)
{
call_once(&aco::init_once_flag, aco::init);
aco::init();
ac_shader_config config = {0};
std::unique_ptr<aco::Program> program{new aco::Program};

100
src/amd/compiler/aco_ir.cpp
View File

@ -22,9 +22,109 @@
*
*/
#include "aco_ir.h"
#include "vulkan/radv_shader.h"
namespace aco {
uint64_t debug_flags = 0;
static const struct debug_control aco_debug_options[] = {
{"validateir", DEBUG_VALIDATE},
{"validatera", DEBUG_VALIDATE_RA},
{"perfwarn", DEBUG_PERFWARN},
{NULL, 0}
};
static once_flag init_once_flag = ONCE_FLAG_INIT;
static void init_once()
{
debug_flags = parse_debug_string(getenv("ACO_DEBUG"), aco_debug_options);
#ifndef NDEBUG
/* enable some flags by default on debug builds */
debug_flags |= aco::DEBUG_VALIDATE;
#endif
}
void init()
{
call_once(&init_once_flag, init_once);
}
void init_program(Program *program, Stage stage, struct radv_shader_info *info,
enum chip_class chip_class, enum radeon_family family,
ac_shader_config *config)
{
program->stage = stage;
program->config = config;
program->info = info;
program->chip_class = chip_class;
if (family == CHIP_UNKNOWN) {
switch (chip_class) {
case GFX6:
program->family = CHIP_TAHITI;
break;
case GFX7:
program->family = CHIP_BONAIRE;
break;
case GFX8:
program->family = CHIP_POLARIS10;
break;
case GFX9:
program->family = CHIP_VEGA10;
break;
case GFX10:
program->family = CHIP_NAVI10;
break;
default:
program->family = CHIP_UNKNOWN;
break;
}
} else {
program->family = family;
}
program->wave_size = info->wave_size;
program->lane_mask = program->wave_size == 32 ? s1 : s2;
program->lds_alloc_granule = chip_class >= GFX7 ? 512 : 256;
program->lds_limit = chip_class >= GFX7 ? 65536 : 32768;
/* apparently gfx702 also has 16-bank LDS but I can't find a family for that */
program->has_16bank_lds = family == CHIP_KABINI || family == CHIP_STONEY;
program->vgpr_limit = 256;
program->vgpr_alloc_granule = 3;
if (chip_class >= GFX10) {
program->physical_sgprs = 2560; /* doesn't matter as long as it's at least 128 * 20 */
program->sgpr_alloc_granule = 127;
program->sgpr_limit = 106;
program->vgpr_alloc_granule = program->wave_size == 32 ? 7 : 3;
} else if (program->chip_class >= GFX8) {
program->physical_sgprs = 800;
program->sgpr_alloc_granule = 15;
if (family == CHIP_TONGA || family == CHIP_ICELAND)
program->sgpr_limit = 94; /* workaround hardware bug */
else
program->sgpr_limit = 102;
} else {
program->physical_sgprs = 512;
program->sgpr_alloc_granule = 7;
program->sgpr_limit = 104;
}
program->next_fp_mode.preserve_signed_zero_inf_nan32 = false;
program->next_fp_mode.preserve_signed_zero_inf_nan16_64 = false;
program->next_fp_mode.must_flush_denorms32 = false;
program->next_fp_mode.must_flush_denorms16_64 = false;
program->next_fp_mode.care_about_round32 = false;
program->next_fp_mode.care_about_round16_64 = false;
program->next_fp_mode.denorm16_64 = fp_denorm_keep;
program->next_fp_mode.denorm32 = 0;
program->next_fp_mode.round16_64 = fp_round_ne;
program->next_fp_mode.round32 = fp_round_ne;
}
bool can_use_SDWA(chip_class chip, const aco_ptr<Instruction>& instr)
{
if (!instr->isVALU())

6
src/amd/compiler/aco_ir.h
View File

@ -1569,6 +1569,12 @@ struct live {
std::vector<std::vector<RegisterDemand>> register_demand;
};
void init();
void init_program(Program *program, Stage stage, struct radv_shader_info *info,
enum chip_class chip_class, enum radeon_family family,
ac_shader_config *config);
void select_program(Program *program,
unsigned shader_count,
struct nir_shader *const *shaders,