From e7470a40c569025b18d4d6767aa21caaa862a5b5 Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Tue, 14 Dec 2021 13:40:49 -0800 Subject: [PATCH] intel/fs: Add physical fall-through CFG edge for unconditional BREAK instruction. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This adds a missing CFG edge that represents a possible physical control flow path the EU might take under some conditions which isn't part of the logical CFG of the program. This possibility shouldn't have led to problems on platforms prior to Gfx12, since the missing control flow edge cannot possibly influence liveness intervals. However on Gfx12+ it becomes the compiler's responsibility to resolve data dependencies across instructions, and the missing physical control flow paths may lead to a WaR data hazard currently not visible to the software scoreboard pass, which could lead to data corruption. Worse, the possibility for this path to be taken by the EU increases on Gfx12+ due to a hardware bug affecting EU fusion -- However the same physical path can be potentially taken on earlier platforms as well, so this patch extends the CFG on all platforms for consistency, even though the lack of this edge shouldn't lead to any functional issues on platforms earlier than Gfx12. There are no shader-db changes on earlier platforms, so there seems to be no disadvantage from using the same CFG representation as on later platforms. This issue has ben reported on TGL with the following conformance test, thanks to Ian for bringing the FULSIM dependency check warning to my attention: dEQP-VK.graphicsfuzz.spv-stable-pillars-volatile-nontemporal-store Fixes: 4d1959e69328cf ("intel/cfg: Represent divergent control flow paths caused by non-uniform loop execution.") Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4940 Reported-by: Tapani Pälli Reported-by: Ian Romanick Reviewed-by: Ian Romanick Part-of: --- src/intel/compiler/brw_cfg.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/intel/compiler/brw_cfg.cpp b/src/intel/compiler/brw_cfg.cpp index 6cbbaaf53c2..4ee8cc82320 100644 --- a/src/intel/compiler/brw_cfg.cpp +++ b/src/intel/compiler/brw_cfg.cpp @@ -364,6 +364,8 @@ cfg_t::cfg_t(const backend_shader *s, exec_list *instructions) : next = new_block(); if (inst->predicate) cur->add_successor(mem_ctx, next, bblock_link_logical); + else + cur->add_successor(mem_ctx, next, bblock_link_physical); set_next_block(&cur, next, ip); break;