freedreno/ir3: add TXD support and expose ARB_shader_texture_lod
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
This commit is contained in:
parent
c49107c889
commit
e6acf3ac24
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@ -179,7 +179,6 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
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case PIPE_CAP_TEXTURE_MULTISAMPLE:
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case PIPE_CAP_TEXTURE_BARRIER:
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case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
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case PIPE_CAP_SM3:
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case PIPE_CAP_CUBE_MAP_ARRAY:
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case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
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case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
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@ -190,6 +189,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
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case PIPE_CAP_COMPUTE:
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return 0;
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case PIPE_CAP_SM3:
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case PIPE_CAP_PRIMITIVE_RESTART:
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return (screen->gpu_id >= 300) ? 1 : 0;
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@ -97,6 +97,8 @@ struct ir3_register {
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int wrmask;
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};
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#define IR3_INSTR_SRCS 10
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struct ir3_instruction {
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struct ir3_block *block;
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int category;
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@ -156,7 +158,7 @@ struct ir3_instruction {
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} flags;
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int repeat;
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unsigned regs_count;
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struct ir3_register *regs[5];
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struct ir3_register *regs[1 + IR3_INSTR_SRCS];
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union {
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struct {
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char inv;
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@ -444,7 +446,7 @@ static inline void regmask_set(regmask_t *regmask, struct ir3_register *reg)
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{
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unsigned idx = regmask_idx(reg);
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unsigned i;
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for (i = 0; i < 4; i++, idx++)
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for (i = 0; i < IR3_INSTR_SRCS; i++, idx++)
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if (reg->wrmask & (1 << i))
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(*regmask)[idx / 8] |= 1 << (idx % 8);
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}
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@ -457,7 +459,7 @@ static inline void regmask_set_if_not(regmask_t *a,
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{
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unsigned idx = regmask_idx(reg);
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unsigned i;
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for (i = 0; i < 4; i++, idx++)
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for (i = 0; i < IR3_INSTR_SRCS; i++, idx++)
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if (reg->wrmask & (1 << i))
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if (!((*b)[idx / 8] & (1 << (idx % 8))))
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(*a)[idx / 8] |= 1 << (idx % 8);
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@ -468,7 +470,7 @@ static inline unsigned regmask_get(regmask_t *regmask,
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{
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unsigned idx = regmask_idx(reg);
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unsigned i;
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for (i = 0; i < 4; i++, idx++)
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for (i = 0; i < IR3_INSTR_SRCS; i++, idx++)
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if (reg->wrmask & (1 << i))
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if ((*regmask)[idx / 8] & (1 << (idx % 8)))
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return true;
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@ -1152,6 +1152,7 @@ fill_tex_info(struct ir3_compile_context *ctx,
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info->flags |= IR3_INSTR_P;
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/* fallthrough */
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case TGSI_OPCODE_TEX:
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case TGSI_OPCODE_TXD:
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info->args = 1;
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break;
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}
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@ -1270,7 +1271,7 @@ trans_samp(const struct instr_translater *t,
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struct ir3_instruction *instr, *collect;
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struct ir3_register *reg;
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struct tgsi_dst_register *dst = &inst->Dst[0].Register;
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struct tgsi_src_register *orig, *coord, *samp, *offset;
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struct tgsi_src_register *orig, *coord, *samp, *offset, *dpdx, *dpdy;
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struct tgsi_src_register zero;
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const struct target_info *tgt = &tex_targets[inst->Texture.Texture];
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struct tex_info tinf;
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@ -1281,12 +1282,25 @@ trans_samp(const struct instr_translater *t,
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coord = get_tex_coord(ctx, inst, &tinf);
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get_immediate(ctx, &zero, 0);
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if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2) {
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switch (inst->Instruction.Opcode) {
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case TGSI_OPCODE_TXB2:
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orig = &inst->Src[1].Register;
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samp = &inst->Src[2].Register;
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} else {
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break;
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case TGSI_OPCODE_TXD:
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orig = &inst->Src[0].Register;
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dpdx = &inst->Src[1].Register;
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dpdy = &inst->Src[2].Register;
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samp = &inst->Src[3].Register;
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if (is_rel_or_const(dpdx))
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dpdx = get_unconst(ctx, dpdx);
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if (is_rel_or_const(dpdy))
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dpdy = get_unconst(ctx, dpdy);
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break;
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default:
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orig = &inst->Src[0].Register;
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samp = &inst->Src[1].Register;
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break;
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}
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if (tinf.args > 1 && is_rel_or_const(orig))
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orig = get_unconst(ctx, orig);
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@ -1311,7 +1325,37 @@ trans_samp(const struct instr_translater *t,
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instr->flags |= tinf.flags;
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add_dst_reg_wrmask(ctx, instr, dst, 0, dst->WriteMask);
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add_src_reg_wrmask(ctx, instr, coord, coord->SwizzleX, tinf.src_wrmask);
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reg = ir3_reg_create(instr, 0, IR3_REG_SSA);
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collect = ir3_instr_create(ctx->block, -1, OPC_META_FI);
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ir3_reg_create(collect, 0, 0);
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for (i = 0; i < 4; i++)
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if (tinf.src_wrmask & (1 << i))
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ssa_src(ctx, ir3_reg_create(collect, 0, IR3_REG_SSA),
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coord, src_swiz(coord, i));
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else if (tinf.src_wrmask & ~((1 << i) - 1))
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ir3_reg_create(collect, 0, 0);
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/* Attach derivatives onto the end of the fan-in. Derivatives start after
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* the 4th argument, so make sure that fi is padded up to 4 first.
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*/
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if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
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while (collect->regs_count < 5)
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ssa_src(ctx, ir3_reg_create(collect, 0, IR3_REG_SSA), &zero, 0);
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for (i = 0; i < tgt->dims; i++)
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ssa_src(ctx, ir3_reg_create(collect, 0, IR3_REG_SSA), dpdx, i);
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if (tgt->dims < 2)
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ssa_src(ctx, ir3_reg_create(collect, 0, IR3_REG_SSA), &zero, 0);
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for (i = 0; i < tgt->dims; i++)
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ssa_src(ctx, ir3_reg_create(collect, 0, IR3_REG_SSA), dpdy, i);
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if (tgt->dims < 2)
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ssa_src(ctx, ir3_reg_create(collect, 0, IR3_REG_SSA), &zero, 0);
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tinf.src_wrmask |= ((1 << (2 * MAX2(tgt->dims, 2))) - 1) << 4;
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}
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reg->instr = collect;
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reg->wrmask = tinf.src_wrmask;
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/* The second argument contains the offsets, followed by the lod/bias
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* argument. This is constructed more manually due to the dynamic nature.
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@ -2485,6 +2529,7 @@ static const struct instr_translater translaters[TGSI_OPCODE_LAST] = {
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INSTR(TXB, trans_samp, .opc = OPC_SAMB, .arg = TGSI_OPCODE_TXB),
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INSTR(TXB2, trans_samp, .opc = OPC_SAMB, .arg = TGSI_OPCODE_TXB2),
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INSTR(TXL, trans_samp, .opc = OPC_SAML, .arg = TGSI_OPCODE_TXL),
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INSTR(TXD, trans_samp, .opc = OPC_SAMGQ, .arg = TGSI_OPCODE_TXD),
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INSTR(TXQ, trans_txq),
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INSTR(DDX, trans_deriv, .opc = OPC_DSX),
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INSTR(DDY, trans_deriv, .opc = OPC_DSY),
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