i965/vec4: Don't register coalesce into source of VS_OPCODE_UNPACK_FLAGS_SIMD4X2
This prevents regressions in a bunch of clipping and interpolation tests caused by the next patch (i965/vec4: Optimize OR with 0 into a MOV). Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
This commit is contained in:
parent
284b563fb0
commit
e6a9bd97b9
|
@ -1285,6 +1285,15 @@ vec4_visitor::opt_register_coalesce()
|
|||
}
|
||||
}
|
||||
|
||||
/* VS_OPCODE_UNPACK_FLAGS_SIMD4X2 generates a bunch of mov(1)
|
||||
* instructions, and this optimization pass is not capable of
|
||||
* handling that. Bail on these instructions and hope that some
|
||||
* later optimization pass can do the right thing after they are
|
||||
* expanded.
|
||||
*/
|
||||
if (scan_inst->opcode == VS_OPCODE_UNPACK_FLAGS_SIMD4X2)
|
||||
break;
|
||||
|
||||
/* This doesn't handle saturation on the instruction we
|
||||
* want to coalesce away if the register types do not match.
|
||||
* But if scan_inst is a non type-converting 'mov', we can fix
|
||||
|
|
Loading…
Reference in New Issue