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radeonsi: move stencil_ref to new handling 

Signed-off-by: Christian König <deathsimple@vodafone.de>
This commit is contained in:
Christian König 2012-07-18 11:03:32 +02:00
parent b41b3eb989
commit e6937211da
7 changed files with 37 additions and 78 deletions
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2
src/gallium/drivers/radeonsi/evergreen_hw_context.c
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@ -59,8 +59,6 @@ static const struct r600_reg si_context_reg_list[] = {
{R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0},
{R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0},
{GROUP_FORCE_NEW_BLOCK, 0},
{R_028430_DB_STENCILREFMASK, 0},
{R_028434_DB_STENCILREFMASK_BF, 0},
{R_028644_SPI_PS_INPUT_CNTL_0, 0},
{R_028648_SPI_PS_INPUT_CNTL_1, 0},
{R_02864C_SPI_PS_INPUT_CNTL_2, 0},

1
src/gallium/drivers/radeonsi/evergreen_state.c
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@ -1072,7 +1072,6 @@ void cayman_init_state_functions(struct r600_context *rctx)
rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
rctx->context.set_sample_mask = evergreen_set_sample_mask;
rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
rctx->context.set_index_buffer = r600_set_index_buffer;
rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;

4
src/gallium/drivers/radeonsi/r600_blit.c
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@ -50,9 +50,7 @@ static void r600_blitter_begin(struct pipe_context *ctx, enum r600_blitter_op op
util_blitter_save_blend(rctx->blitter, rctx->queued.named.blend);
util_blitter_save_depth_stencil_alpha(rctx->blitter, rctx->queued.named.dsa);
if (rctx->states[R600_PIPE_STATE_STENCIL_REF]) {
util_blitter_save_stencil_ref(rctx->blitter, &rctx->stencil_ref);
}
util_blitter_save_stencil_ref(rctx->blitter, &rctx->stencil_ref);
util_blitter_save_rasterizer(rctx->blitter, rctx->queued.named.rasterizer);
util_blitter_save_fragment_shader(rctx->blitter, rctx->ps_shader);
util_blitter_save_vertex_shader(rctx->blitter, rctx->vs_shader);

50
src/gallium/drivers/radeonsi/r600_state_common.c
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@ -120,56 +120,6 @@ static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
}
/* common state between evergreen and r600 */
void r600_set_stencil_ref(struct pipe_context *ctx,
const struct r600_stencil_ref *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
if (rstate == NULL)
return;
rstate->id = R600_PIPE_STATE_STENCIL_REF;
r600_pipe_state_add_reg(rstate,
R_028430_DB_STENCILREFMASK,
S_028430_STENCILTESTVAL(state->ref_value[0]) |
S_028430_STENCILMASK(state->valuemask[0]) |
S_028430_STENCILWRITEMASK(state->writemask[0]),
NULL, 0);
r600_pipe_state_add_reg(rstate,
R_028434_DB_STENCILREFMASK_BF,
S_028434_STENCILTESTVAL_BF(state->ref_value[1]) |
S_028434_STENCILMASK_BF(state->valuemask[1]) |
S_028434_STENCILWRITEMASK_BF(state->writemask[1]),
NULL, 0);
free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
r600_context_pipe_state_set(rctx, rstate);
}
void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
const struct pipe_stencil_ref *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct si_state_dsa *dsa = rctx->queued.named.dsa;
struct r600_stencil_ref ref;
rctx->stencil_ref = *state;
if (!dsa)
return;
ref.ref_value[0] = state->ref_value[0];
ref.ref_value[1] = state->ref_value[1];
ref.valuemask[0] = dsa->valuemask[0];
ref.valuemask[1] = dsa->valuemask[1];
ref.writemask[0] = dsa->writemask[0];
ref.writemask[1] = dsa->writemask[1];
r600_set_stencil_ref(ctx, &ref);
}
void r600_sampler_view_destroy(struct pipe_context *ctx,
struct pipe_sampler_view *state)
{

12
src/gallium/drivers/radeonsi/radeonsi_pipe.h
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@ -78,7 +78,6 @@ enum r600_pipe_state_id {
R600_PIPE_STATE_CONFIG,
R600_PIPE_STATE_SEAMLESS_CUBEMAP,
R600_PIPE_STATE_VGT,
R600_PIPE_STATE_STENCIL_REF,
R600_PIPE_STATE_PS_SHADER,
R600_PIPE_STATE_VS_SHADER,
R600_PIPE_STATE_CONSTANT,
@ -189,13 +188,6 @@ struct r600_fence_block {
#define R600_CONSTANT_ARRAY_SIZE 256
#define R600_RESOURCE_ARRAY_SIZE 160
struct r600_stencil_ref
{
ubyte ref_value[2];
ubyte valuemask[2];
ubyte writemask[2];
};
struct r600_context {
struct pipe_context context;
struct blitter_context *blitter;
@ -400,10 +392,6 @@ void r600_set_so_targets(struct pipe_context *ctx,
unsigned num_targets,
struct pipe_stream_output_target **targets,
unsigned append_bitmask);
void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
const struct pipe_stencil_ref *state);
void r600_set_stencil_ref(struct pipe_context *ctx,
const struct r600_stencil_ref *state);
void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
/*

45
src/gallium/drivers/radeonsi/si_state.c
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@ -465,6 +465,39 @@ static void si_delete_rs_state(struct pipe_context *ctx, void *state)
si_pm4_delete_state(rctx, rasterizer, (struct si_state_rasterizer *)state);
}
/*
* infeered state between dsa and stencil ref
*/
static void si_update_dsa_stencil_ref(struct r600_context *rctx)
{
struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
struct pipe_stencil_ref *ref = &rctx->stencil_ref;
struct si_state_dsa *dsa = rctx->queued.named.dsa;
if (pm4 == NULL)
return;
si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
S_028430_STENCILTESTVAL(ref->ref_value[0]) |
S_028430_STENCILMASK(dsa->valuemask[0]) |
S_028430_STENCILWRITEMASK(dsa->writemask[0]));
si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]));
si_pm4_set_state(rctx, dsa_stencil_ref, pm4);
}
static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
const struct pipe_stencil_ref *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
rctx->stencil_ref = *state;
si_update_dsa_stencil_ref(rctx);
}
/*
* DSA
*/
@ -550,25 +583,16 @@ static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct si_state_dsa *dsa = state;
struct r600_stencil_ref ref;
if (state == NULL)
return;
si_pm4_bind_state(rctx, dsa, dsa);
si_update_dsa_stencil_ref(rctx);
// TODO
rctx->alpha_ref = dsa->alpha_ref;
rctx->alpha_ref_dirty = true;
ref.ref_value[0] = rctx->stencil_ref.ref_value[0];
ref.ref_value[1] = rctx->stencil_ref.ref_value[1];
ref.valuemask[0] = dsa->valuemask[0];
ref.valuemask[1] = dsa->valuemask[1];
ref.writemask[0] = dsa->writemask[0];
ref.writemask[1] = dsa->writemask[1];
r600_set_stencil_ref(ctx, &ref);
}
static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
@ -1264,6 +1288,7 @@ void si_init_state_functions(struct r600_context *rctx)
rctx->context.set_clip_state = si_set_clip_state;
rctx->context.set_scissor_state = si_set_scissor_state;
rctx->context.set_viewport_state = si_set_viewport_state;
rctx->context.set_stencil_ref = si_set_pipe_stencil_ref;
rctx->context.set_framebuffer_state = si_set_framebuffer_state;
}

1
src/gallium/drivers/radeonsi/si_state.h
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@ -72,6 +72,7 @@ union si_state {
struct si_state_rasterizer *rasterizer;
struct si_state_dsa *dsa;
struct si_pm4_state *fb_rs;
struct si_pm4_state *dsa_stencil_ref;
} named;
struct si_pm4_state *array[0];
};