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intel/disasm: add missing handling of <1;1,0> 

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 7cd9adeb41 ("intel/compiler: In XeHP prefer <1;1,0> regions before compacting")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16704>
This commit is contained in:
Lionel Landwerlin 2022-05-25 14:17:03 +03:00 committed by Marge Bot
parent c219ca3fb7
commit e666089082
1 changed files with 1 additions and 0 deletions
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src/intel/compiler/brw_disasm.c
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@ -1216,6 +1216,7 @@ implied_width(enum brw_vertical_stride _vert_stride,
/* "2. Width is equal to vertical stride when Horizontal Stride is zero." */
} else if (_horiz_stride == BRW_HORIZONTAL_STRIDE_0) {
switch (_vert_stride) {
case BRW_VERTICAL_STRIDE_1: return BRW_WIDTH_1;
case BRW_VERTICAL_STRIDE_2: return BRW_WIDTH_2;
case BRW_VERTICAL_STRIDE_4: return BRW_WIDTH_4;
case BRW_VERTICAL_STRIDE_8: return BRW_WIDTH_8;