radeonsi: Adapt to sample intrinsics changes.
Fix up intrinsic names, and bitcast texture address parameters to integers. NOTE: This is a candidate for the 9.1 branch.
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624528834f
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e5fb7347a7
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@ -155,7 +155,7 @@ static inline LLVMValueRef bitcast(
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void radeon_llvm_emit_prepare_cube_coords(struct lp_build_tgsi_context * bld_base,
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struct lp_build_emit_data * emit_data,
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unsigned coord_arg);
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LLVMValueRef *coords_arg);
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void radeon_llvm_context_init(struct radeon_llvm_context * ctx);
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@ -531,7 +531,7 @@ static void kil_emit(
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void radeon_llvm_emit_prepare_cube_coords(
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struct lp_build_tgsi_context * bld_base,
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struct lp_build_emit_data * emit_data,
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unsigned coord_arg)
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LLVMValueRef *coords_arg)
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{
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unsigned target = emit_data->inst->Texture.Texture;
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@ -542,11 +542,13 @@ void radeon_llvm_emit_prepare_cube_coords(
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LLVMValueRef coords[4];
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LLVMValueRef mad_args[3];
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LLVMValueRef idx;
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struct LLVMOpaqueValue *cube_vec;
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LLVMValueRef v;
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unsigned i;
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LLVMValueRef v = build_intrinsic(builder, "llvm.AMDGPU.cube",
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LLVMVectorType(type, 4),
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&emit_data->args[coord_arg], 1, LLVMReadNoneAttribute);
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cube_vec = lp_build_gather_values(bld_base->base.gallivm, coords_arg, 4);
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v = build_intrinsic(builder, "llvm.AMDGPU.cube", LLVMVectorType(type, 4),
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&cube_vec, 1, LLVMReadNoneAttribute);
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for (i = 0; i < 4; ++i) {
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idx = lp_build_const_int32(gallivm, i);
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@ -579,18 +581,14 @@ void radeon_llvm_emit_prepare_cube_coords(
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if (target != TGSI_TEXTURE_CUBE ||
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opcode != TGSI_OPCODE_TEX) {
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/* load source coord.w component - array_index for cube arrays or
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* compare value for SHADOWCUBE */
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idx = lp_build_const_int32(gallivm, 3);
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coords[3] = LLVMBuildExtractElement(builder,
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emit_data->args[coord_arg], idx, "");
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/* for cube arrays coord.z = coord.w(array_index) * 8 + face */
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if (target == TGSI_TEXTURE_CUBE_ARRAY ||
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target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
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/* coords_arg.w component - array_index for cube arrays or
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* compare value for SHADOWCUBE */
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coords[2] = lp_build_emit_llvm_ternary(bld_base, TGSI_OPCODE_MAD,
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coords[3], lp_build_const_float(gallivm, 8.0), coords[2]);
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coords_arg[3], lp_build_const_float(gallivm, 8.0), coords[2]);
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}
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/* for instructions that need additional src (compare/lod/bias),
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@ -598,12 +596,11 @@ void radeon_llvm_emit_prepare_cube_coords(
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if (opcode == TGSI_OPCODE_TEX2 ||
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opcode == TGSI_OPCODE_TXB2 ||
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opcode == TGSI_OPCODE_TXL2) {
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coords[3] = emit_data->args[coord_arg + 1];
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coords[3] = coords_arg[4];
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}
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}
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emit_data->args[coord_arg] =
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lp_build_gather_values(bld_base->base.gallivm, coords, 4);
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memcpy(coords_arg, coords, sizeof(coords));
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}
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static void txd_fetch_args(
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@ -645,9 +642,6 @@ static void txp_fetch_args(
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TGSI_OPCODE_DIV, arg, src_w);
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}
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coords[3] = bld_base->base.one;
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emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm,
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coords, 4);
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emit_data->arg_count = 1;
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if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
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inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
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@ -655,8 +649,12 @@ static void txp_fetch_args(
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inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
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inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
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inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
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radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, 0);
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radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
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}
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emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm,
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coords, 4);
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emit_data->arg_count = 1;
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}
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static void tex_fetch_args(
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@ -673,17 +671,12 @@ static void tex_fetch_args(
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const struct tgsi_full_instruction * inst = emit_data->inst;
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LLVMValueRef coords[4];
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LLVMValueRef coords[5];
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unsigned chan;
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for (chan = 0; chan < 4; chan++) {
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coords[chan] = lp_build_emit_fetch(bld_base, inst, 0, chan);
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}
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emit_data->arg_count = 1;
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emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm,
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coords, 4);
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emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
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if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
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inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
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inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
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@ -692,7 +685,7 @@ static void tex_fetch_args(
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* That operand should be passed as a float value in the args array
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* right after the coord vector. After packing it's not used anymore,
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* that's why arg_count is not increased */
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emit_data->args[1] = lp_build_emit_fetch(bld_base, inst, 1, 0);
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coords[4] = lp_build_emit_fetch(bld_base, inst, 1, 0);
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}
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if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
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@ -701,8 +694,13 @@ static void tex_fetch_args(
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inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
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inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
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inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
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radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, 0);
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radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
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}
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emit_data->arg_count = 1;
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emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm,
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coords, 4);
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emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
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}
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static void txf_fetch_args(
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@ -791,9 +791,12 @@ static void tex_fetch_args(
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struct lp_build_tgsi_context * bld_base,
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struct lp_build_emit_data * emit_data)
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{
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struct gallivm_state *gallivm = bld_base->base.gallivm;
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const struct tgsi_full_instruction * inst = emit_data->inst;
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LLVMValueRef ptr;
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LLVMValueRef offset;
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LLVMValueRef coords[5];
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unsigned chan;
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/* WriteMask */
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/* XXX: should be optimized using emit_data->inst->Dst[0].Register.WriteMask*/
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@ -801,27 +804,22 @@ static void tex_fetch_args(
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/* Coordinates */
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/* XXX: Not all sample instructions need 4 address arguments. */
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if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
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LLVMValueRef src_w;
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unsigned chan;
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LLVMValueRef coords[4];
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emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
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src_w = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
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if (inst->Instruction.Opcode == TGSI_OPCODE_TXP)
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coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W)
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;
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for (chan = 0; chan < 3; chan++ ) {
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LLVMValueRef arg = lp_build_emit_fetch(bld_base,
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emit_data->inst, 0, chan);
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coords[chan] = lp_build_emit_fetch(bld_base,
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emit_data->inst, 0,
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chan);
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if (inst->Instruction.Opcode == TGSI_OPCODE_TXP)
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coords[chan] = lp_build_emit_llvm_binary(bld_base,
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TGSI_OPCODE_DIV,
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arg, src_w);
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coords[chan],
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coords[3]);
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}
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coords[3] = bld_base->base.one;
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emit_data->args[1] = lp_build_gather_values(bld_base->base.gallivm,
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coords, 4);
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} else
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emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst,
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0, LP_CHAN_ALL);
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if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
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inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
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@ -831,15 +829,24 @@ static void tex_fetch_args(
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* That operand should be passed as a float value in the args array
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* right after the coord vector. After packing it's not used anymore,
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* that's why arg_count is not increased */
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emit_data->args[2] = lp_build_emit_fetch(bld_base, inst, 1, 0);
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coords[4] = lp_build_emit_fetch(bld_base, inst, 1, 0);
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}
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if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
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inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE) &&
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inst->Instruction.Opcode != TGSI_OPCODE_TXQ) {
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radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, 1);
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radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
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}
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for (chan = 0; chan < 4; chan++ ) {
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coords[chan] = LLVMBuildBitCast(gallivm->builder,
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coords[chan],
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LLVMInt32TypeInContext(gallivm->context),
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"");
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}
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emit_data->args[1] = lp_build_gather_values(gallivm, coords, 4);
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/* Resource */
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ptr = use_sgpr(bld_base->base.gallivm, SGPR_CONST_PTR_V8I32, SI_SGPR_RESOURCE);
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offset = lp_build_const_int32(bld_base->base.gallivm,
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@ -869,19 +876,19 @@ static void tex_fetch_args(
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static const struct lp_build_tgsi_action tex_action = {
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.fetch_args = tex_fetch_args,
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.emit = lp_build_tgsi_intrinsic,
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.intr_name = "llvm.SI.sample"
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.intr_name = "llvm.SI.sample."
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};
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static const struct lp_build_tgsi_action txb_action = {
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.fetch_args = tex_fetch_args,
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.emit = lp_build_tgsi_intrinsic,
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.intr_name = "llvm.SI.sample.bias"
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.intr_name = "llvm.SI.sampleb."
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};
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static const struct lp_build_tgsi_action txl_action = {
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.fetch_args = tex_fetch_args,
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.emit = lp_build_tgsi_intrinsic,
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.intr_name = "llvm.SI.sample.lod"
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.intr_name = "llvm.SI.samplel."
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};
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