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i965: limit VF caching workaround to gen8/9/10 

Documentation of the 3DSTATE_VERTEX_BUFFERS packet says this is only
needed before ICL.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Lionel Landwerlin 2019-01-03 16:13:14 +00:00
parent f0312cfa93
commit e5ed217545
2 changed files with 4 additions and 2 deletions
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2
src/mesa/drivers/dri/i965/genX_blorp_exec.c
View File

@ -197,7 +197,7 @@ blorp_vf_invalidate_for_vb_48b_transitions(struct blorp_batch *batch,
const struct blorp_address *addrs,
unsigned num_vbs)
{
#if GEN_GEN >= 8
#if GEN_GEN >= 8 && GEN_GEN < 11
struct brw_context *brw = batch->driver_batch;
bool need_invalidate = false;

4
src/mesa/drivers/dri/i965/genX_state_upload.c
View File

@ -530,11 +530,13 @@ pinned_bo_high_bits(struct brw_bo *bo)
* In the relocation world, we have no idea what the addresses will be, so
* we can't apply this workaround. Instead, we tell the kernel to move it
* to the low 4GB regardless.
*
* This HW issue is gone on Gen11+.
*/
static void
vf_invalidate_for_vb_48bit_transitions(struct brw_context *brw)
{
#if GEN_GEN >= 8
#if GEN_GEN >= 8 && GEN_GEN < 11
bool need_invalidate = false;
unsigned i;