pan/mdg: Replace zext with a type enum
The index type is actually a two-bit field, with support for both sign and zero extension. What was previously labelled as `zext` actually does sign-extension, but we want that in most cases anyway. Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8264>
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@ -36,11 +36,17 @@
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* This allows for fast indexing into arrays. This file tries to pattern match the offset in NIR with this form to reduce pressure on the ALU pipe.
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*/
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enum index_type {
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ITYPE_U64 = 1 << 6,
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ITYPE_U32 = 2 << 6, // zero-extend
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ITYPE_I32 = 3 << 6, // sign-extend
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};
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struct mir_address {
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nir_ssa_scalar A;
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nir_ssa_scalar B;
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bool zext;
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enum index_type type;
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unsigned shift;
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unsigned bias;
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};
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@ -105,7 +111,7 @@ mir_match_iadd(struct mir_address *address, bool first_free)
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}
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}
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/* Matches u2u64 and sets zext */
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/* Matches u2u64 and sets type */
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static void
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mir_match_u2u64(struct mir_address *address)
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@ -121,7 +127,7 @@ mir_match_u2u64(struct mir_address *address)
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nir_ssa_scalar arg = nir_ssa_scalar_chase_alu_src(address->B, 0);
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address->B = arg;
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address->zext = true;
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address->type = ITYPE_U32;
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}
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/* Matches ishl to shift */
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@ -175,7 +181,8 @@ static struct mir_address
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mir_match_offset(nir_ssa_def *offset, bool first_free)
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{
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struct mir_address address = {
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.B = { .def = offset }
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.B = { .def = offset },
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.type = ITYPE_U64,
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};
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mir_match_mov(&address);
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@ -198,15 +205,19 @@ mir_set_offset(compiler_context *ctx, midgard_instruction *ins, nir_src *offset,
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ins->swizzle[2][i] = 0;
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}
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bool force_zext = (nir_src_bit_size(*offset) < 64);
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/* Sign extend instead of zero extend in case the address is something
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* like `base + offset + 20`, where offset could be negative. */
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bool force_sext = (nir_src_bit_size(*offset) < 64);
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if (!offset->is_ssa) {
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ins->load_store.arg_1 |= is_shared ? 0x6E : 0x7E;
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ins->src[2] = nir_src_index(ctx, offset);
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ins->src_types[2] = nir_type_uint | nir_src_bit_size(*offset);
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if (force_zext)
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ins->load_store.arg_1 |= 0x80;
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if (force_sext)
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ins->load_store.arg_1 |= ITYPE_I32;
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else
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ins->load_store.arg_1 |= ITYPE_U64;
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return;
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}
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@ -227,8 +238,10 @@ mir_set_offset(compiler_context *ctx, midgard_instruction *ins, nir_src *offset,
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} else
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ins->load_store.arg_2 = 0x1E;
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if (match.zext || force_zext)
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ins->load_store.arg_1 |= 0x80;
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if (force_sext)
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match.type = ITYPE_I32;
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ins->load_store.arg_1 |= match.type;
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assert(match.shift <= 7);
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ins->load_store.arg_2 |= (match.shift) << 5;
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