KonstantinSeurer
/
mesa
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

nir/lower_task_shader: don't use base index for shared memory intrinsics 

Intel backend doesn't handle them very well.

Fixes: 8aff8d3dd4 ("nir: Add common task shader lowering to make the backend's job easier.")
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17143>
This commit is contained in:
Timur Kristóf 2022-06-20 17:31:06 +02:00 committed by Marge Bot
parent 49b8fffeed
commit e5970fe22a
1 changed files with 4 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
src/compiler/nir/nir_lower_task_shader.c
View File

@ -55,8 +55,7 @@ lower_nv_task_output(nir_builder *b,
case nir_intrinsic_load_output: {
b->cursor = nir_after_instr(instr);
nir_ssa_def *load =
nir_load_shared(b, 1, 32, nir_imm_int(b, 0),
.base = s->task_count_shared_addr);
nir_load_shared(b, 1, 32, nir_imm_int(b, s->task_count_shared_addr));
nir_ssa_def_rewrite_uses(&intrin->dest.ssa, load);
nir_instr_remove(instr);
return true;
@ -65,8 +64,7 @@ lower_nv_task_output(nir_builder *b,
case nir_intrinsic_store_output: {
b->cursor = nir_after_instr(instr);
nir_ssa_def *store_val = intrin->src[0].ssa;
nir_store_shared(b, store_val, nir_imm_int(b, 0),
.base = s->task_count_shared_addr);
nir_store_shared(b, store_val, nir_imm_int(b, s->task_count_shared_addr));
nir_instr_remove(instr);
return true;
}
@ -86,7 +84,7 @@ append_launch_mesh_workgroups_to_nv_task(nir_builder *b,
*/
b->cursor = nir_before_cf_list(&b->impl->body);
nir_ssa_def *zero = nir_imm_int(b, 0);
nir_store_shared(b, zero, zero, .base = s->task_count_shared_addr);
nir_store_shared(b, zero, nir_imm_int(b, s->task_count_shared_addr));
nir_scoped_barrier(b,
.execution_scope = NIR_SCOPE_WORKGROUP,
@ -106,7 +104,7 @@ append_launch_mesh_workgroups_to_nv_task(nir_builder *b,
.memory_modes = nir_var_mem_shared);
nir_ssa_def *task_count =
nir_load_shared(b, 1, 32, zero, .base = s->task_count_shared_addr);
nir_load_shared(b, 1, 32, nir_imm_int(b, s->task_count_shared_addr));
/* NV_mesh_shader doesn't offer to choose which task_payload variable
* should be passed to mesh shaders, we just pass all.