winsys/amdgpu: update amdgpu_addr_create for GFX9
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
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@ -36,6 +36,9 @@
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#define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
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#define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
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#endif
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#endif
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#ifndef CIASICIDGFXENGINE_ARCTICISLAND
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#define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
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#endif
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static int amdgpu_surface_sanity(const struct pipe_resource *tex)
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static int amdgpu_surface_sanity(const struct pipe_resource *tex)
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{
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{
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@ -107,32 +110,41 @@ ADDR_HANDLE amdgpu_addr_create(struct amdgpu_winsys *ws)
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addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
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addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
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addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
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addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
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regValue.noOfBanks = ws->amdinfo.mc_arb_ramcfg & 0x3;
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regValue.gbAddrConfig = ws->amdinfo.gb_addr_cfg;
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regValue.gbAddrConfig = ws->amdinfo.gb_addr_cfg;
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regValue.noOfRanks = (ws->amdinfo.mc_arb_ramcfg & 0x4) >> 2;
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createFlags.value = 0;
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regValue.backendDisables = ws->amdinfo.enabled_rb_pipes_mask;
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if (ws->info.chip_class >= GFX9) {
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regValue.pTileConfig = ws->amdinfo.gb_tile_mode;
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addrCreateInput.chipEngine = CIASICIDGFXENGINE_ARCTICISLAND;
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regValue.noOfEntries = ARRAY_SIZE(ws->amdinfo.gb_tile_mode);
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regValue.blockVarSizeLog2 = 0;
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if (ws->info.chip_class == SI) {
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regValue.pMacroTileConfig = NULL;
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regValue.noOfMacroEntries = 0;
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} else {
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} else {
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regValue.pMacroTileConfig = ws->amdinfo.gb_macro_tile_mode;
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regValue.noOfBanks = ws->amdinfo.mc_arb_ramcfg & 0x3;
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regValue.noOfMacroEntries = ARRAY_SIZE(ws->amdinfo.gb_macro_tile_mode);
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regValue.noOfRanks = (ws->amdinfo.mc_arb_ramcfg & 0x4) >> 2;
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regValue.backendDisables = ws->amdinfo.enabled_rb_pipes_mask;
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regValue.pTileConfig = ws->amdinfo.gb_tile_mode;
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regValue.noOfEntries = ARRAY_SIZE(ws->amdinfo.gb_tile_mode);
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if (ws->info.chip_class == SI) {
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regValue.pMacroTileConfig = NULL;
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regValue.noOfMacroEntries = 0;
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} else {
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regValue.pMacroTileConfig = ws->amdinfo.gb_macro_tile_mode;
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regValue.noOfMacroEntries = ARRAY_SIZE(ws->amdinfo.gb_macro_tile_mode);
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}
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createFlags.useTileIndex = 1;
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createFlags.useHtileSliceAlign = 1;
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addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
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addrCreateInput.chipFamily = ws->family;
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addrCreateInput.chipRevision = ws->rev_id;
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}
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}
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createFlags.value = 0;
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createFlags.useTileIndex = 1;
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createFlags.useHtileSliceAlign = 1;
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addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
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addrCreateInput.chipFamily = ws->family;
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addrCreateInput.chipFamily = ws->family;
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addrCreateInput.chipRevision = ws->rev_id;
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addrCreateInput.chipRevision = ws->rev_id;
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addrCreateInput.createFlags = createFlags;
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addrCreateInput.callbacks.allocSysMem = allocSysMem;
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addrCreateInput.callbacks.allocSysMem = allocSysMem;
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addrCreateInput.callbacks.freeSysMem = freeSysMem;
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addrCreateInput.callbacks.freeSysMem = freeSysMem;
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addrCreateInput.callbacks.debugPrint = 0;
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addrCreateInput.callbacks.debugPrint = 0;
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addrCreateInput.createFlags = createFlags;
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addrCreateInput.regValue = regValue;
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addrCreateInput.regValue = regValue;
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addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
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addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
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