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radeon/vce: increase cpb height alignment 

Height should be aligned with 2 macroblocks, thus making safer
for tiled mode

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
This commit is contained in:
Leo Liu 2016-07-04 11:29:28 -04:00
parent fa0654fc3c
commit e560a11b87
1 changed files with 1 additions and 1 deletions
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2
src/gallium/drivers/radeon/radeon_vce.c
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@ -454,7 +454,7 @@ struct pipe_video_codec *rvce_create_encoder(struct pipe_context *context,
get_buffer(((struct vl_video_buffer *)tmp_buf)->resources[0], NULL, &tmp_surf);
cpb_size = align(tmp_surf->level[0].pitch_bytes, 128);
cpb_size = cpb_size * align(tmp_surf->npix_y, 16);
cpb_size = cpb_size * align(tmp_surf->npix_y, 32);
cpb_size = cpb_size * 3 / 2;
cpb_size = cpb_size * enc->cpb_num;
if (enc->dual_pipe)