KonstantinSeurer
/
mesa
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

ilo: use only defines from genhw headers 

Stop including classic driver headers in genhw.h, with some formatting fixes.
This commit is contained in:
Chia-I Wu 2014-04-13 20:07:40 +08:00
parent 6c6bd796ad
commit e55e1610e5
7 changed files with 87 additions and 106 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/gallium/drivers/ilo/genhw/genhw.h
View File

@ -28,9 +28,6 @@
#include "pipe/p_compiler.h"
#include "util/u_debug.h"
#include "intel_reg.h"
#include "brw_defines.h"
#include "gen_regs.xml.h"
#include "gen_mi.xml.h"
#include "gen_blitter.xml.h"

43
src/gallium/drivers/ilo/ilo_blitter_blt.c
View File

@ -35,13 +35,12 @@
#include "ilo_resource.h"
#include "ilo_blitter.h"
#ifndef COLOR_BLT_CMD
#define COLOR_BLT_CMD (CMD_2D | (0x40 << 22))
#endif
#ifndef SRC_COPY_BLT_CMD
#define SRC_COPY_BLT_CMD (CMD_2D | (0x43 << 22))
#endif
#define MI_FLUSH_DW GEN_MI_CMD(MI_FLUSH_DW)
#define MI_LOAD_REGISTER_IMM GEN_MI_CMD(MI_LOAD_REGISTER_IMM)
#define COLOR_BLT GEN_BLITTER_CMD(COLOR_BLT)
#define XY_COLOR_BLT GEN_BLITTER_CMD(XY_COLOR_BLT)
#define SRC_COPY_BLT GEN_BLITTER_CMD(SRC_COPY_BLT)
#define XY_SRC_COPY_BLT GEN_BLITTER_CMD(XY_SRC_COPY_BLT)
enum gen6_blt_mask {
GEN6_BLT_MASK_8,
@ -137,7 +136,7 @@ gen6_emit_COLOR_BLT(struct ilo_dev_info *dev,
const int cpp = gen6_translate_blt_cpp(value_mask);
uint32_t dw0, dw1;
dw0 = COLOR_BLT_CMD |
dw0 = COLOR_BLT |
gen6_translate_blt_write_mask(write_mask) |
(cmd_len - 2);
@ -146,7 +145,7 @@ gen6_emit_COLOR_BLT(struct ilo_dev_info *dev,
/* offsets are naturally aligned and pitches are dword-aligned */
assert(dst_offset % cpp == 0 && dst_pitch % 4 == 0);
dw1 = rop << 16 |
dw1 = rop << GEN6_BLITTER_BR13_ROP__SHIFT |
gen6_translate_blt_value_mask(value_mask) |
dst_pitch;
@ -176,7 +175,7 @@ gen6_emit_XY_COLOR_BLT(struct ilo_dev_info *dev,
int dst_align, dst_pitch_shift;
uint32_t dw0, dw1;
dw0 = XY_COLOR_BLT_CMD |
dw0 = XY_COLOR_BLT |
gen6_translate_blt_write_mask(write_mask) |
(cmd_len - 2);
@ -196,7 +195,7 @@ gen6_emit_XY_COLOR_BLT(struct ilo_dev_info *dev,
assert(y2 - y1 < gen6_max_scanlines);
assert(dst_offset % dst_align == 0 && dst_pitch % dst_align == 0);
dw1 = rop << 16 |
dw1 = rop << GEN6_BLITTER_BR13_ROP__SHIFT |
gen6_translate_blt_value_mask(value_mask) |
dst_pitch >> dst_pitch_shift;
@ -227,7 +226,7 @@ gen6_emit_SRC_COPY_BLT(struct ilo_dev_info *dev,
const int cpp = gen6_translate_blt_cpp(value_mask);
uint32_t dw0, dw1;
dw0 = SRC_COPY_BLT_CMD |
dw0 = SRC_COPY_BLT |
gen6_translate_blt_write_mask(write_mask) |
(cmd_len - 2);
@ -237,12 +236,12 @@ gen6_emit_SRC_COPY_BLT(struct ilo_dev_info *dev,
assert(dst_offset % cpp == 0 && dst_pitch % 4 == 0);
assert(src_offset % cpp == 0 && src_pitch % 4 == 0);
dw1 = rop << 16 |
dw1 = rop << GEN6_BLITTER_BR13_ROP__SHIFT |
gen6_translate_blt_value_mask(value_mask) |
dst_pitch;
if (dir_rtl)
dw1 |= 1 << 30;
dw1 |= GEN6_BLITTER_BR13_DIR_RTL;
ilo_cp_begin(cp, cmd_len);
ilo_cp_write(cp, dw0);
@ -275,7 +274,7 @@ gen6_emit_XY_SRC_COPY_BLT(struct ilo_dev_info *dev,
int src_align, src_pitch_shift;
uint32_t dw0, dw1;
dw0 = XY_SRC_COPY_BLT_CMD |
dw0 = XY_SRC_COPY_BLT |
gen6_translate_blt_write_mask(write_mask) |
(cmd_len - 2);
@ -308,7 +307,7 @@ gen6_emit_XY_SRC_COPY_BLT(struct ilo_dev_info *dev,
assert(dst_offset % dst_align == 0 && dst_pitch % dst_align == 0);
assert(src_offset % src_align == 0 && src_pitch % src_align == 0);
dw1 = rop << 16 |
dw1 = rop << GEN6_BLITTER_BR13_ROP__SHIFT |
gen6_translate_blt_value_mask(value_mask) |
dst_pitch >> dst_pitch_shift;
@ -352,7 +351,7 @@ ilo_blitter_blt_begin(struct ilo_blitter *blitter, int max_cmd_size,
if (!intel_winsys_can_submit_bo(ilo->winsys, aper_check, count))
ilo_cp_flush(ilo->cp, "out of aperture");
/* set GEN6_REG_BCS_SWCTRL */
/* set BCS_SWCTRL */
swctrl = 0x0;
if (dst_tiling == INTEL_TILING_Y) {
@ -368,7 +367,7 @@ ilo_blitter_blt_begin(struct ilo_blitter *blitter, int max_cmd_size,
if (swctrl) {
/*
* Most clients expect BLT engine to be stateless. If we have to set
* GEN6_REG_BCS_SWCTRL to a non-default value, we have to set it back in the same
* BCS_SWCTRL to a non-default value, we have to set it back in the same
* batch buffer.
*/
if (ilo_cp_space(ilo->cp) < (4 + 3) * 2 + max_cmd_size)
@ -383,9 +382,11 @@ ilo_blitter_blt_begin(struct ilo_blitter *blitter, int max_cmd_size,
* this bit (Tile Y Destination/Source)."
*/
gen6_emit_MI_FLUSH_DW(ilo->dev, ilo->cp);
gen6_emit_MI_LOAD_REGISTER_IMM(ilo->dev, GEN6_REG_BCS_SWCTRL, swctrl, ilo->cp);
gen6_emit_MI_LOAD_REGISTER_IMM(ilo->dev,
GEN6_REG_BCS_SWCTRL, swctrl, ilo->cp);
swctrl &= ~(GEN6_REG_BCS_SWCTRL_DST_TILING_Y | GEN6_REG_BCS_SWCTRL_SRC_TILING_Y);
swctrl &= ~(GEN6_REG_BCS_SWCTRL_DST_TILING_Y |
GEN6_REG_BCS_SWCTRL_SRC_TILING_Y);
}
return swctrl;
@ -396,7 +397,7 @@ ilo_blitter_blt_end(struct ilo_blitter *blitter, uint32_t swctrl)
{
struct ilo_context *ilo = blitter->ilo;
/* set GEN6_REG_BCS_SWCTRL back */
/* set BCS_SWCTRL back */
if (swctrl) {
gen6_emit_MI_FLUSH_DW(ilo->dev, ilo->cp);
gen6_emit_MI_LOAD_REGISTER_IMM(ilo->dev, GEN6_REG_BCS_SWCTRL, swctrl, ilo->cp);

5
src/gallium/drivers/ilo/ilo_cp.c
View File

@ -25,11 +25,14 @@
* Chia-I Wu <olv@lunarg.com>
*/
#include "genhw/genhw.h" /* for MI_xxx */
#include "genhw/genhw.h"
#include "intel_winsys.h"
#include "ilo_cp.h"
#define MI_NOOP GEN_MI_CMD(MI_NOOP)
#define MI_BATCH_BUFFER_END GEN_MI_CMD(MI_BATCH_BUFFER_END)
/* the size of the private space */
static const int ilo_cp_private = 2;

53
src/gallium/drivers/ilo/ilo_gpe_gen6.h
View File

@ -138,14 +138,14 @@ ilo_gpe_gen6_translate_winsys_tiling(enum intel_tiling_mode tiling)
{
switch (tiling) {
case INTEL_TILING_NONE:
return 0;
return GEN6_TILING_NONE;
case INTEL_TILING_X:
return GEN6_TILING_X;
case INTEL_TILING_Y:
return GEN6_TILING_Y;
default:
assert(!"unknown tiling");
return 0;
return GEN6_TILING_NONE;
}
}
@ -275,12 +275,7 @@ ilo_gpe_gen6_fill_3dstate_sf_sbe(const struct ilo_dev_info *dev,
if (!fs) {
memset(dw, 0, sizeof(dw[0]) * num_dwords);
if (dev->gen >= ILO_GEN(7))
dw[0] = 1 << GEN7_SBE_DW1_URB_READ_LEN__SHIFT;
else
dw[0] = 1 << GEN7_SBE_DW1_URB_READ_LEN__SHIFT;
dw[0] = 1 << GEN7_SBE_DW1_URB_READ_LEN__SHIFT;
return;
}
@ -297,20 +292,11 @@ ilo_gpe_gen6_fill_3dstate_sf_sbe(const struct ilo_dev_info *dev,
if (!vue_len)
vue_len = 1;
if (dev->gen >= ILO_GEN(7)) {
dw[0] = output_count << GEN7_SBE_DW1_ATTR_COUNT__SHIFT |
vue_len << GEN7_SBE_DW1_URB_READ_LEN__SHIFT |
vue_offset << GEN7_SBE_DW1_URB_READ_OFFSET__SHIFT;
if (routing->swizzle_enable)
dw[0] |= GEN7_SBE_DW1_ATTR_SWIZZLE_ENABLE;
}
else {
dw[0] = output_count << GEN7_SBE_DW1_ATTR_COUNT__SHIFT |
vue_len << GEN7_SBE_DW1_URB_READ_LEN__SHIFT |
vue_offset << GEN7_SBE_DW1_URB_READ_OFFSET__SHIFT;
if (routing->swizzle_enable)
dw[0] |= GEN7_SBE_DW1_ATTR_SWIZZLE_ENABLE;
}
dw[0] = output_count << GEN7_SBE_DW1_ATTR_COUNT__SHIFT |
vue_len << GEN7_SBE_DW1_URB_READ_LEN__SHIFT |
vue_offset << GEN7_SBE_DW1_URB_READ_OFFSET__SHIFT;
if (routing->swizzle_enable)
dw[0] |= GEN7_SBE_DW1_ATTR_SWIZZLE_ENABLE;
switch (rasterizer->state.sprite_coord_mode) {
case PIPE_SPRITE_COORD_UPPER_LEFT:
@ -914,9 +900,7 @@ ve_set_cso_edgeflag(const struct ilo_dev_info *dev,
*/
format = (cso->payload[0] >> GEN6_VE_STATE_DW0_FORMAT__SHIFT) & 0x1ff;
if (format == GEN6_FORMAT_R32_FLOAT) {
STATIC_ASSERT(GEN6_FORMAT_R32_UINT ==
GEN6_FORMAT_R32_FLOAT - 1);
STATIC_ASSERT(GEN6_FORMAT_R32_UINT == GEN6_FORMAT_R32_FLOAT - 1);
cso->payload[0] -= (1 << GEN6_VE_STATE_DW0_FORMAT__SHIFT);
}
else {
@ -1022,17 +1006,17 @@ gen6_emit_3DSTATE_INDEX_BUFFER(const struct ilo_dev_info *dev,
switch (ib->hw_index_size) {
case 4:
format = GEN6_IB_DW0_FORMAT_DWORD >> GEN6_IB_DW0_FORMAT__SHIFT;
format = GEN6_IB_DW0_FORMAT_DWORD;
break;
case 2:
format = GEN6_IB_DW0_FORMAT_WORD >> GEN6_IB_DW0_FORMAT__SHIFT;
format = GEN6_IB_DW0_FORMAT_WORD;
break;
case 1:
format = GEN6_IB_DW0_FORMAT_BYTE >> GEN6_IB_DW0_FORMAT__SHIFT;
format = GEN6_IB_DW0_FORMAT_BYTE;
break;
default:
assert(!"unknown index size");
format = GEN6_IB_DW0_FORMAT_BYTE >> GEN6_IB_DW0_FORMAT__SHIFT;
format = GEN6_IB_DW0_FORMAT_BYTE;
break;
}
@ -1050,7 +1034,7 @@ gen6_emit_3DSTATE_INDEX_BUFFER(const struct ilo_dev_info *dev,
ilo_cp_begin(cp, cmd_len);
ilo_cp_write(cp, cmd | (cmd_len - 2) |
((enable_cut_index) ? GEN6_IB_DW0_CUT_INDEX_ENABLE : 0) |
format << 8);
format);
ilo_cp_write_bo(cp, start_offset, buf->bo, INTEL_DOMAIN_VERTEX, 0);
ilo_cp_write_bo(cp, end_offset, buf->bo, INTEL_DOMAIN_VERTEX, 0);
ilo_cp_end(cp);
@ -1355,10 +1339,8 @@ gen6_emit_3DSTATE_WM(const struct ilo_dev_info *dev,
assert(!hiz_op);
dw4 |= GEN6_WM_DW4_STATISTICS;
if (cc_may_kill) {
dw5 |= GEN6_WM_DW5_PS_KILL |
GEN6_WM_DW5_PS_ENABLE;
}
if (cc_may_kill)
dw5 |= GEN6_WM_DW5_PS_KILL | GEN6_WM_DW5_PS_ENABLE;
if (dual_blend)
dw5 |= GEN6_WM_DW5_DUAL_SOURCE_BLEND;
@ -1960,8 +1942,7 @@ gen6_emit_3DPRIMITIVE(const struct ilo_dev_info *dev,
const int prim = (rectlist) ?
GEN6_3DPRIM_RECTLIST : ilo_gpe_gen6_translate_pipe_prim(info->mode);
const int vb_access = (info->indexed) ?
GEN6_3DPRIM_DW0_ACCESS_RANDOM :
GEN6_3DPRIM_DW0_ACCESS_SEQUENTIAL;
GEN6_3DPRIM_DW0_ACCESS_RANDOM : GEN6_3DPRIM_DW0_ACCESS_SEQUENTIAL;
const uint32_t vb_start = info->start +
((info->indexed) ? ib->draw_start_offset : 0);

74
src/gallium/drivers/ilo/ilo_gpe_gen7.c
View File

@ -33,6 +33,8 @@
#include "ilo_shader.h"
#include "ilo_gpe_gen7.h"
#define SET_FIELD(value, field) (((value) << field ## __SHIFT) & field ## __MASK)
void
ilo_gpe_init_gs_cso_gen7(const struct ilo_dev_info *dev,
const struct ilo_shader_state *gs,
@ -63,14 +65,14 @@ ilo_gpe_init_gs_cso_gen7(const struct ilo_dev_info *dev,
dw2 = (true) ? 0 : GEN6_THREADDISP_FP_MODE_ALT;
dw4 = vue_read_len << GEN6_GS_DW4_URB_READ_LEN__SHIFT |
dw4 = vue_read_len << GEN7_GS_DW4_URB_READ_LEN__SHIFT |
GEN7_GS_DW4_INCLUDE_VERTEX_HANDLES |
0 << GEN6_GS_DW4_URB_READ_OFFSET__SHIFT |
start_grf << GEN6_GS_DW4_URB_GRF_START__SHIFT;
0 << GEN7_GS_DW4_URB_READ_OFFSET__SHIFT |
start_grf << GEN7_GS_DW4_URB_GRF_START__SHIFT;
dw5 = (max_threads - 1) << GEN6_GS_DW5_MAX_THREADS__SHIFT |
GEN6_GS_DW5_STATISTICS |
GEN6_GS_DW6_GS_ENABLE;
dw5 = (max_threads - 1) << GEN7_GS_DW5_MAX_THREADS__SHIFT |
GEN7_GS_DW5_STATISTICS |
GEN7_GS_DW5_GS_ENABLE;
STATIC_ASSERT(Elements(cso->payload) >= 3);
cso->payload[0] = dw2;
@ -275,16 +277,16 @@ ilo_gpe_init_view_surface_null_gen7(const struct ilo_dev_info *dev,
STATIC_ASSERT(Elements(surf->payload) >= 8);
dw = surf->payload;
dw[0] = GEN6_SURFTYPE_NULL << GEN6_SURFACE_DW0_TYPE__SHIFT |
GEN6_FORMAT_B8G8R8A8_UNORM << GEN6_SURFACE_DW0_FORMAT__SHIFT |
dw[0] = GEN6_SURFTYPE_NULL << GEN7_SURFACE_DW0_TYPE__SHIFT |
GEN6_FORMAT_B8G8R8A8_UNORM << GEN7_SURFACE_DW0_FORMAT__SHIFT |
GEN6_TILING_X << 13;
dw[1] = 0;
dw[2] = SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT) |
SET_FIELD(width - 1, GEN7_SURFACE_WIDTH);
dw[2] = SET_FIELD(height - 1, GEN7_SURFACE_DW2_HEIGHT) |
SET_FIELD(width - 1, GEN7_SURFACE_DW2_WIDTH);
dw[3] = SET_FIELD(depth - 1, BRW_SURFACE_DEPTH);
dw[3] = SET_FIELD(depth - 1, GEN7_SURFACE_DW3_DEPTH);
dw[4] = 0;
dw[5] = level;
@ -314,7 +316,7 @@ ilo_gpe_init_view_surface_for_buffer_gen7(const struct ilo_dev_info *dev,
ILO_GPE_VALID_GEN(dev, 7, 7.5);
surface_type = (structured) ? 5 : GEN6_SURFTYPE_BUFFER;
surface_type = (structured) ? GEN7_SURFTYPE_STRBUF : GEN6_SURFTYPE_BUFFER;
surface_format = (typed) ?
ilo_translate_color_format(elem_format) : GEN6_FORMAT_RAW;
@ -390,17 +392,17 @@ ilo_gpe_init_view_surface_for_buffer_gen7(const struct ilo_dev_info *dev,
STATIC_ASSERT(Elements(surf->payload) >= 8);
dw = surf->payload;
dw[0] = surface_type << GEN6_SURFACE_DW0_TYPE__SHIFT |
surface_format << GEN6_SURFACE_DW0_FORMAT__SHIFT;
dw[0] = surface_type << GEN7_SURFACE_DW0_TYPE__SHIFT |
surface_format << GEN7_SURFACE_DW0_FORMAT__SHIFT;
if (render_cache_rw)
dw[0] |= GEN6_SURFACE_DW0_RENDER_CACHE_RW;
dw[0] |= GEN7_SURFACE_DW0_RENDER_CACHE_RW;
dw[1] = offset;
dw[2] = SET_FIELD(height, GEN7_SURFACE_HEIGHT) |
SET_FIELD(width, GEN7_SURFACE_WIDTH);
dw[2] = SET_FIELD(height, GEN7_SURFACE_DW2_HEIGHT) |
SET_FIELD(width, GEN7_SURFACE_DW2_WIDTH);
dw[3] = SET_FIELD(depth, BRW_SURFACE_DEPTH) |
dw[3] = SET_FIELD(depth, GEN7_SURFACE_DW3_DEPTH) |
pitch;
dw[4] = 0;
@ -410,10 +412,10 @@ ilo_gpe_init_view_surface_for_buffer_gen7(const struct ilo_dev_info *dev,
dw[7] = 0;
if (dev->gen >= ILO_GEN(7.5)) {
dw[7] |= SET_FIELD(GEN75_SCS_RED, GEN7_SURFACE_SCS_R) |
SET_FIELD(GEN75_SCS_GREEN, GEN7_SURFACE_SCS_G) |
SET_FIELD(GEN75_SCS_BLUE, GEN7_SURFACE_SCS_B) |
SET_FIELD(GEN75_SCS_ALPHA, GEN7_SURFACE_SCS_A);
dw[7] |= SET_FIELD(GEN75_SCS_RED, GEN75_SURFACE_DW7_SCS_R) |
SET_FIELD(GEN75_SCS_GREEN, GEN75_SURFACE_DW7_SCS_G) |
SET_FIELD(GEN75_SCS_BLUE, GEN75_SURFACE_DW7_SCS_B) |
SET_FIELD(GEN75_SCS_ALPHA, GEN75_SURFACE_DW7_SCS_A);
}
/* do not increment reference count */
@ -580,8 +582,8 @@ ilo_gpe_init_view_surface_for_texture_gen7(const struct ilo_dev_info *dev,
STATIC_ASSERT(Elements(surf->payload) >= 8);
dw = surf->payload;
dw[0] = surface_type << GEN6_SURFACE_DW0_TYPE__SHIFT |
surface_format << GEN6_SURFACE_DW0_FORMAT__SHIFT |
dw[0] = surface_type << GEN7_SURFACE_DW0_TYPE__SHIFT |
surface_format << GEN7_SURFACE_DW0_FORMAT__SHIFT |
ilo_gpe_gen6_translate_winsys_tiling(tex->tiling) << 13;
/*
@ -614,17 +616,17 @@ ilo_gpe_init_view_surface_for_texture_gen7(const struct ilo_dev_info *dev,
dw[0] |= GEN7_SURFACE_DW0_ARYSPC_LOD0;
if (is_rt)
dw[0] |= GEN6_SURFACE_DW0_RENDER_CACHE_RW;
dw[0] |= GEN7_SURFACE_DW0_RENDER_CACHE_RW;
if (surface_type == GEN6_SURFTYPE_CUBE && !is_rt)
dw[0] |= GEN6_SURFACE_DW0_CUBE_FACE_ENABLES__MASK;
dw[0] |= GEN7_SURFACE_DW0_CUBE_FACE_ENABLES__MASK;
dw[1] = layer_offset;
dw[2] = SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT) |
SET_FIELD(width - 1, GEN7_SURFACE_WIDTH);
dw[2] = SET_FIELD(height - 1, GEN7_SURFACE_DW2_HEIGHT) |
SET_FIELD(width - 1, GEN7_SURFACE_DW2_WIDTH);
dw[3] = SET_FIELD(depth - 1, BRW_SURFACE_DEPTH) |
dw[3] = SET_FIELD(depth - 1, GEN7_SURFACE_DW3_DEPTH) |
(pitch - 1);
dw[4] = first_layer << 18 |
@ -650,19 +652,19 @@ ilo_gpe_init_view_surface_for_texture_gen7(const struct ilo_dev_info *dev,
else
dw[4] |= GEN7_SURFACE_DW4_MULTISAMPLECOUNT_1;
dw[5] = x_offset << GEN6_SURFACE_DW5_X_OFFSET__SHIFT |
y_offset << GEN6_SURFACE_DW5_Y_OFFSET__SHIFT |
SET_FIELD(first_level, GEN7_SURFACE_MIN_LOD) |
dw[5] = x_offset << GEN7_SURFACE_DW5_X_OFFSET__SHIFT |
y_offset << GEN7_SURFACE_DW5_Y_OFFSET__SHIFT |
SET_FIELD(first_level, GEN7_SURFACE_DW5_MIN_LOD) |
lod;
dw[6] = 0;
dw[7] = 0;
if (dev->gen >= ILO_GEN(7.5)) {
dw[7] |= SET_FIELD(GEN75_SCS_RED, GEN7_SURFACE_SCS_R) |
SET_FIELD(GEN75_SCS_GREEN, GEN7_SURFACE_SCS_G) |
SET_FIELD(GEN75_SCS_BLUE, GEN7_SURFACE_SCS_B) |
SET_FIELD(GEN75_SCS_ALPHA, GEN7_SURFACE_SCS_A);
dw[7] |= SET_FIELD(GEN75_SCS_RED, GEN75_SURFACE_DW7_SCS_R) |
SET_FIELD(GEN75_SCS_GREEN, GEN75_SURFACE_DW7_SCS_G) |
SET_FIELD(GEN75_SCS_BLUE, GEN75_SURFACE_DW7_SCS_B) |
SET_FIELD(GEN75_SCS_ALPHA, GEN75_SURFACE_DW7_SCS_A);
}
/* do not increment reference count */

8
src/gallium/drivers/ilo/ilo_gpe_gen7.h
View File

@ -233,7 +233,7 @@ gen7_emit_3DSTATE_GS(const struct ilo_dev_info *dev,
ilo_cp_write(cp, 0);
ilo_cp_write(cp, 0);
ilo_cp_write(cp, 0);
ilo_cp_write(cp, GEN6_GS_DW5_STATISTICS);
ilo_cp_write(cp, GEN7_GS_DW5_STATISTICS);
ilo_cp_write(cp, 0);
ilo_cp_end(cp);
return;
@ -313,10 +313,8 @@ gen7_emit_3DSTATE_WM(const struct ilo_dev_info *dev,
dw1 |= fs_cso->payload[3];
}
if (cc_may_kill) {
dw1 |= GEN7_WM_DW1_PS_ENABLE |
GEN7_WM_DW1_PS_KILL;
}
if (cc_may_kill)
dw1 |= GEN7_WM_DW1_PS_ENABLE | GEN7_WM_DW1_PS_KILL;
if (num_samples > 1) {
dw1 |= rasterizer->wm.dw_msaa_rast;

7
src/gallium/drivers/ilo/ilo_shader.c
View File

@ -309,8 +309,8 @@ ilo_shader_variant_init(struct ilo_shader_variant *variant,
/*
* When non-nearest filter and PIPE_TEX_WRAP_CLAMP wrap mode is used,
* the HW wrap mode is set to GEN6_TEXCOORDMODE_CLAMP_BORDER, and we need
* to manually saturate the texture coordinates.
* the HW wrap mode is set to GEN6_TEXCOORDMODE_CLAMP_BORDER, and we
* need to manually saturate the texture coordinates.
*/
if (sampler) {
variant->saturate_tex_coords[0] |= sampler->saturate_s << i;
@ -991,8 +991,7 @@ ilo_shader_select_kernel_routing(struct ilo_shader_state *shader,
src_slot + 1 < routing->source_len &&
src_semantics[src_slot + 1] == TGSI_SEMANTIC_BCOLOR &&
src_indices[src_slot + 1] == index) {
routing->swizzles[dst_slot] |= ATTRIBUTE_SWIZZLE_INPUTATTR_FACING <<
ATTRIBUTE_SWIZZLE_SHIFT;
routing->swizzles[dst_slot] |= GEN7_SBE_ATTR_INPUTATTR_FACING;
src_slot++;
}