Revert "i965: Always use Y-tiled buffers on SKL+"
This commit broke Weston, Mutter, and xf86-video-modesetting, on KMS.
In order to use Y-tiled buffers, the kernel requires the tiling mode to
be explicitly named through the I915_FORMAT_MOD_Y_TILED AddFB2 modifier;
it disallows any attempt to infer the buffer's tiling mode.
As the GBM API does not have a way to extract modifiers for a buffer,
this commit broke all users of GBM on SKL+. Revert it for now, until we
get a way to extract modifier information from GBM, and also let GBM
users inform the implementation that it intends to use the modifiers.
This reverts commit 6a0d036483
.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Acked-by: Ben Widawsky <ben@bwidawsk.net>
Tested-by: Hans de Goede <hdegoede@redhat.com>
This commit is contained in:
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@ -244,7 +244,7 @@ brw_get_fast_clear_rect(const struct brw_context *brw,
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* alignment size returned by intel_get_non_msrt_mcs_alignment(), but
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* with X alignment multiplied by 16 and Y alignment multiplied by 32.
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*/
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intel_get_non_msrt_mcs_alignment(brw, mt, &x_align, &y_align);
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intel_get_non_msrt_mcs_alignment(mt, &x_align, &y_align);
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x_align *= 16;
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/* SKL+ line alignment requirement for Y-tiled are half those of the prior
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@ -838,7 +838,7 @@ brw_get_resolve_rect(const struct brw_context *brw,
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* by a factor of 2.
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*/
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intel_get_non_msrt_mcs_alignment(brw, mt, &x_align, &y_align);
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intel_get_non_msrt_mcs_alignment(mt, &x_align, &y_align);
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if (brw->gen >= 9) {
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x_scaledown = x_align * 8;
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y_scaledown = y_align * 8;
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@ -144,8 +144,7 @@ compute_msaa_layout(struct brw_context *brw, mesa_format format,
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* by half the block width, and Y coordinates by half the block height.
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*/
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void
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intel_get_non_msrt_mcs_alignment(const struct brw_context *brw,
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const struct intel_mipmap_tree *mt,
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intel_get_non_msrt_mcs_alignment(const struct intel_mipmap_tree *mt,
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unsigned *width_px, unsigned *height)
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{
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switch (mt->tiling) {
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@ -157,11 +156,6 @@ intel_get_non_msrt_mcs_alignment(const struct brw_context *brw,
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*height = 4;
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break;
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case I915_TILING_X:
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/* The docs are somewhat confusing with the way the tables are displayed.
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* However, it does clearly state: "MCS and Lossless compression is
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* supported for TiledY/TileYs/TileYf non-MSRTs only."
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*/
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assert(brw->gen < 9);
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*width_px = 64 / mt->cpp;
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*height = 2;
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}
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@ -1558,7 +1552,7 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
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const mesa_format format = MESA_FORMAT_R_UINT32;
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unsigned block_width_px;
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unsigned block_height;
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intel_get_non_msrt_mcs_alignment(brw, mt, &block_width_px, &block_height);
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intel_get_non_msrt_mcs_alignment(mt, &block_width_px, &block_height);
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unsigned width_divisor = block_width_px * 4;
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unsigned height_divisor = block_height * 8;
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@ -663,8 +663,7 @@ struct intel_mipmap_tree
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};
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void
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intel_get_non_msrt_mcs_alignment(const struct brw_context *brw,
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const struct intel_mipmap_tree *mt,
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intel_get_non_msrt_mcs_alignment(const struct intel_mipmap_tree *mt,
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unsigned *width_px, unsigned *height);
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bool
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@ -516,11 +516,7 @@ intel_create_image(__DRIscreen *screen,
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int cpp;
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unsigned long pitch;
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if (intelScreen->devinfo->gen >= 9) {
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tiling = I915_TILING_Y;
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} else {
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tiling = I915_TILING_X;
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}
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tiling = I915_TILING_X;
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if (use & __DRI_IMAGE_USE_CURSOR) {
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if (width != 64 || height != 64)
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return NULL;
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@ -1148,14 +1144,8 @@ intel_detect_swizzling(struct intel_screen *screen)
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drm_intel_bo *buffer;
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unsigned long flags = 0;
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unsigned long aligned_pitch;
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uint32_t tiling = I915_TILING_X;
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uint32_t swizzle_mode = 0;
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uint32_t tiling;
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if (screen->devinfo->gen >= 9) {
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tiling = I915_TILING_Y;
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} else {
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tiling = I915_TILING_X;
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}
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buffer = drm_intel_bo_alloc_tiled(screen->bufmgr, "swizzle test",
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64, 64, 4,
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@ -1581,12 +1571,7 @@ intelAllocateBuffer(__DRIscreen *screen,
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return NULL;
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/* The front and back buffers are color buffers, which are X tiled. */
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uint32_t tiling;
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if (intelScreen->devinfo->gen >= 9) {
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tiling = I915_TILING_Y;
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} else {
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tiling = I915_TILING_X;
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}
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uint32_t tiling = I915_TILING_X;
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unsigned long pitch;
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int cpp = format / 8;
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intelBuffer->bo = drm_intel_bo_alloc_tiled(intelScreen->bufmgr,
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