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nouveau/nv50: disable GLSL IR loop unrolling 

NIR loop unrolling is already enabled so just let it do its job.

Shader-db results (nv92):

total gpr in shared programs: 734638 -> 735037 (0.05%)
gpr in affected programs: 11058 -> 11457 (3.61%)
total instructions in shared programs: 6073415 -> 6073398 (<.01%)
instructions in affected programs: 10079 -> 10062 (-0.17%)
total bytes in shared programs: 41837432 -> 41838872 (<.01%)
bytes in affected programs: 252504 -> 253944 (0.57%)

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16366>
This commit is contained in:
Timothy Arceri 2022-05-06 11:50:42 +10:00 committed by Marge Bot
parent fa3b6a3d32
commit e5181c2e23
4 changed files with 20 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/gallium/drivers/nouveau/nv50/nv50_screen.c
View File

@ -515,10 +515,9 @@ nv50_screen_get_shader_param(struct pipe_screen *pscreen,
return shader == PIPE_SHADER_COMPUTE ? NV50_MAX_GLOBALS - 1 : 0;
case PIPE_SHADER_CAP_PREFERRED_IR:
return screen->prefer_nir ? PIPE_SHADER_IR_NIR : PIPE_SHADER_IR_TGSI;
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
return 32;
case PIPE_SHADER_CAP_SUPPORTED_IRS:
return (1 << PIPE_SHADER_IR_TGSI) | (1 << PIPE_SHADER_IR_NIR);
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
case PIPE_SHADER_CAP_DROUND_SUPPORTED:
case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED:
case PIPE_SHADER_CAP_LDEXP_SUPPORTED:
@ -995,7 +994,7 @@ nv50_screen_get_compiler_options(struct pipe_screen *pscreen,
enum pipe_shader_type shader)
{
if (ir == PIPE_SHADER_IR_NIR)
return nv50_ir_nir_shader_compiler_options(NVISA_G80_CHIPSET);
return nv50_ir_nir_shader_compiler_options(NVISA_G80_CHIPSET, shader);
return NULL;
}

3
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
View File

@ -1028,7 +1028,8 @@ nvc0_screen_get_compiler_options(struct pipe_screen *pscreen,
{
struct nvc0_screen *screen = nvc0_screen(pscreen);
if (ir == PIPE_SHADER_IR_NIR)
return nv50_ir_nir_shader_compiler_options(screen->base.device->chipset);
return nv50_ir_nir_shader_compiler_options(screen->base.device->chipset,
shader);
return NULL;
}

2
src/nouveau/codegen/nv50_ir_driver.h
View File

@ -220,7 +220,7 @@ extern "C" {
#endif
const struct nir_shader_compiler_options *
nv50_ir_nir_shader_compiler_options(int chipset);
nv50_ir_nir_shader_compiler_options(int chipset, uint8_t shader_type);
extern int nv50_ir_generate_code(struct nv50_ir_prog_info *,
struct nv50_ir_prog_info_out *);

22
src/nouveau/codegen/nv50_ir_from_nir.cpp
View File

@ -3298,7 +3298,7 @@ Program::makeFromNIR(struct nv50_ir_prog_info *info,
} // namespace nv50_ir
static nir_shader_compiler_options
nvir_nir_shader_compiler_options(int chipset)
nvir_nir_shader_compiler_options(int chipset, uint8_t shader_type)
{
nir_shader_compiler_options op = {};
op.lower_fdiv = (chipset >= NVISA_GV100_CHIPSET);
@ -3379,6 +3379,8 @@ nvir_nir_shader_compiler_options(int chipset)
op.lower_rotate = (chipset < NVISA_GV100_CHIPSET);
op.has_imul24 = false;
op.intel_vec4 = false;
op.force_indirect_unrolling = (nir_variable_mode)
((shader_type == PIPE_SHADER_FRAGMENT) ? nir_var_shader_out : 0);
op.force_indirect_unrolling_sampler = (chipset < NVISA_GF100_CHIPSET),
op.max_unroll_iterations = 32;
op.lower_int64_options = (nir_lower_int64_options) (
@ -3410,16 +3412,18 @@ nvir_nir_shader_compiler_options(int chipset)
}
static const nir_shader_compiler_options g80_nir_shader_compiler_options =
nvir_nir_shader_compiler_options(NVISA_G80_CHIPSET);
nvir_nir_shader_compiler_options(NVISA_G80_CHIPSET, PIPE_SHADER_TYPES);
static const nir_shader_compiler_options g80_fs_nir_shader_compiler_options =
nvir_nir_shader_compiler_options(NVISA_G80_CHIPSET, PIPE_SHADER_FRAGMENT);
static const nir_shader_compiler_options gf100_nir_shader_compiler_options =
nvir_nir_shader_compiler_options(NVISA_GF100_CHIPSET);
nvir_nir_shader_compiler_options(NVISA_GF100_CHIPSET, PIPE_SHADER_TYPES);
static const nir_shader_compiler_options gm107_nir_shader_compiler_options =
nvir_nir_shader_compiler_options(NVISA_GM107_CHIPSET);
nvir_nir_shader_compiler_options(NVISA_GM107_CHIPSET, PIPE_SHADER_TYPES);
static const nir_shader_compiler_options gv100_nir_shader_compiler_options =
nvir_nir_shader_compiler_options(NVISA_GV100_CHIPSET);
nvir_nir_shader_compiler_options(NVISA_GV100_CHIPSET, PIPE_SHADER_TYPES);
const nir_shader_compiler_options *
nv50_ir_nir_shader_compiler_options(int chipset)
nv50_ir_nir_shader_compiler_options(int chipset, uint8_t shader_type)
{
if (chipset >= NVISA_GV100_CHIPSET)
return &gv100_nir_shader_compiler_options;
@ -3427,5 +3431,9 @@ nv50_ir_nir_shader_compiler_options(int chipset)
return &gm107_nir_shader_compiler_options;
if (chipset >= NVISA_GF100_CHIPSET)
return &gf100_nir_shader_compiler_options;
return &g80_nir_shader_compiler_options;
if (shader_type == PIPE_SHADER_FRAGMENT)
return &g80_fs_nir_shader_compiler_options;
else
return &g80_nir_shader_compiler_options;
}