panfrost/midgard: Remove assembler
This code is outdated and unused; now that the compiler is mature, there's no point keeping it around in-tree (or at all). Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This commit is contained in:
Alyssa Rosenzweig
parent
2cd1aa3429
commit
e4ec814c39
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@ -1,643 +0,0 @@
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"""
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Copyright (C) 2018 Alyssa Rosenzweig
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Copyright (c) 2013 Connor Abbott (connor@abbott.cx)
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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import sys
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import pprint
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import struct
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program = []
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# Definitions from cwabbott's tools
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t6xx_alu_ops = {
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"fadd": 0x10,
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"fmul": 0x14,
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"fmin": 0x28,
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"fmax": 0x2C,
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"fmov": 0x30,
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"ffloor": 0x36,
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"fceil": 0x37,
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"fdot3": 0x3C,
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"fdot3r": 0x3D,
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"fdot4": 0x3E,
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"freduce": 0x3F,
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"iadd": 0x40,
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"isub": 0x46,
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"imul": 0x58,
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"imov": 0x7B,
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"feq": 0x80,
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"fne": 0x81,
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"flt": 0x82,
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"fle": 0x83,
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"f2i": 0x99,
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"f2u8": 0x9C,
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"u2f": 0xBC,
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"ieq": 0xA0,
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"ine": 0xA1,
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"ilt": 0xA4,
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"ile": 0xA5,
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"iand": 0x70,
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"ior": 0x71,
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"inot": 0x72,
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"iandnot": 0x74,
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"ixor": 0x76,
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"ball": 0xA9,
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"bany": 0xB1,
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"i2f": 0xB8,
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"csel": 0xC5,
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"fatan_pt2": 0xE8,
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"frcp": 0xF0,
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"frsqrt": 0xF2,
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"fsqrt": 0xF3,
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"fexp2": 0xF4,
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"flog2": 0xF5,
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"fsin": 0xF6,
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"fcos": 0xF7,
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"fatan2_pt1": 0xF9,
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}
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t6xx_alu_bits = {
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"vmul": 17,
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"sadd": 19,
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"vadd": 21,
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"smul": 23,
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"lut": 25,
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"br": 26,
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"branch": 27,
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"constants": 32
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}
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t6xx_alu_size_bits = {
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"vmul": 48,
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"sadd": 32,
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"vadd": 48,
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"smul": 32,
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"lut": 48,
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"br": 16,
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"branch": 48
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}
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t6xx_outmod = {
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"none": 0,
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"pos": 1,
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"int": 2,
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"sat": 3
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}
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t6xx_reg_mode = {
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"quarter": 0,
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"half": 1,
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"full": 2,
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"double": 3
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}
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t6xx_dest_override = {
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"lower": 0,
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"upper": 1,
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"none": 2
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}
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t6xx_load_store_ops = {
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"ld_st_noop": 0x03,
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"ld_attr_16": 0x95,
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"ld_attr_32": 0x94,
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"ld_vary_16": 0x99,
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"ld_vary_32": 0x98,
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"ld_uniform_16": 0xAC,
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"ld_uniform_32": 0xB0,
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"st_vary_16": 0xD5,
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"st_vary_32": 0xD4,
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"ld_color_buffer_8": 0xBA
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}
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t6xx_tag = {
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"texture": 0x3,
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"load_store": 0x5,
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"alu4": 0x8,
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"alu8": 0x9,
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"alu12": 0xA,
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"alu16": 0xB,
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}
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def is_tag_alu(tag):
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return (tag >= t6xx_tag["alu4"]) and (tag <= t6xx_tag["alu16"])
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# Just an enum
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ALU = 0
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LDST = 1
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TEXTURE = 2
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# Constant types supported, mapping the constant prefix to the Python format
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# string and the coercion function
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constant_types = {
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"f": ("f", float),
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"h": ("e", float),
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"i": ("i", int),
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"s": ("h", int)
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}
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compact_branch_op = {
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"jump": 1,
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"branch": 2,
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"discard": 4,
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"write": 7
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}
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branch_condition = {
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"false": 1,
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"true": 2,
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"always": 3,
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}
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# TODO: What else?
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texture_op = {
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"normal": 0x11,
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"texelfetch": 0x14
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}
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texture_fmt = {
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"2d": 0x02,
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"3d": 0x03
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}
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with open(sys.argv[1], "r") as f:
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for ln in f:
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space = ln.strip().split(" ")
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instruction = space[0]
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rest = " ".join(space[1:])
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arguments = [s.strip() for s in rest.split(",")]
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program += [(instruction, arguments)]
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swizzle_component = {
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"x": 0,
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"y": 1,
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"z": 2,
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"w": 3
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}
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def decode_reg_name(reg_name):
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ireg = 0
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upper = False
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half = False
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if reg_name[0] == 'r':
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ireg = int(reg_name[1:])
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elif reg_name[0] == 'h':
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rreg = int(reg_name[2:])
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# Decode half-register into its full register's half
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ireg = rreg >> 1
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upper = rreg & 1
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half = True
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else:
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# Special case for load/store addresses
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ireg = int(reg_name)
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return (ireg, half, upper)
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def standard_swizzle_from_parts(swizzle_parts):
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swizzle_s = swizzle_parts[1] if len(swizzle_parts) > 1 else "xyzw"
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swizzle = 0
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for (i, c) in enumerate(swizzle_s):
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swizzle |= swizzle_component[c] << (2 * i)
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return swizzle
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def mask_from_parts(mask_parts, large_mask):
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mask_s = mask_parts[1] if len(mask_parts) > 1 else "xyzw"
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if large_mask:
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mask = sum([(3 << (2*swizzle_component[c]) if c in mask_s else 0) for c in "xyzw"])
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else:
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mask = sum([(1 << swizzle_component[c] if c in mask_s else 0) for c in "xyzw"])
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return (mask, mask_s)
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def decode_reg(reg):
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if reg[0] == "#":
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# Not actually a register, instead an immediate float
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return (True, struct.unpack("H", struct.pack("e", float(reg[1:])))[0], 0, 0, 0, 0)
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# Function call syntax used in abs() modifier
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if reg[-1] == ')':
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reg = reg[:-1]
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swizzle_parts = reg.split(".")
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reg_name = swizzle_parts[0]
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modifiers = 0
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if reg_name[0] == '-':
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modifiers |= 2
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reg_name = reg_name[1:]
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if reg_name[0] == 'a':
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modifiers |= 1
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reg_name = reg_name[len("abs("):]
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(ireg, half, upper) = decode_reg_name(reg_name)
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return (False, ireg, standard_swizzle_from_parts(swizzle_parts), half, upper, modifiers)
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def decode_masked_reg(reg, large_mask):
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mask_parts = reg.split(".")
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reg_name = mask_parts[0]
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(ireg, half, upper) = decode_reg_name(reg_name)
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(mask, mask_s) = mask_from_parts(mask_parts, large_mask)
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component = max([0] + [swizzle_component[c] for c in "xyzw" if c in mask_s])
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return (ireg, mask, component, half, upper)
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# TODO: Fill these in XXX
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# Texture pipeline registers in r28-r29
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TEXTURE_BASE = 28
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def decode_texture_reg_number(reg):
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r = reg.split(".")[0]
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if r[0] == "r":
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return (True, int(r[1:]) - TEXTURE_BASE, 0)
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else:
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no = int(r[2:])
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return (False, (no >> 1) - TEXTURE_BASE, no & 1)
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def decode_texture_reg(reg):
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(full, select, upper) = decode_texture_reg_number(reg)
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# Swizzle mandatory for texture registers, afaict
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swizzle = reg.split(".")[1]
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swizzleL = swizzle_component[swizzle[0]]
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swizzleR = swizzle_component[swizzle[1]]
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return (full, select, upper, swizzleR, swizzleL)
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def decode_texture_out_reg(reg):
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(full, select, upper) = decode_texture_reg_number(reg)
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(mask, _) = mask_from_parts(reg.split("."), False)
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return (full, select, upper, mask)
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instruction_stream = []
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for p in program:
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ins = p[0]
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arguments = p[1]
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family = ins_mod = ins.split(".")[0]
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ins_op = (ins + ".").split(".")[1]
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ins_outmod = (ins + "." + ".").split(".")[2]
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try:
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out_mod = t6xx_outmod[ins_outmod]
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except:
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out_mod = 0
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if ins in t6xx_load_store_ops:
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op = t6xx_load_store_ops[ins]
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(reg, mask, component, half, upper) = decode_masked_reg(p[1][0], False)
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(immediate, address, swizzle, half, upper, modifiers) = decode_reg(p[1][1])
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unknown = int(p[1][2], 16)
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b = (op << 0) | (reg << 8) | (mask << 13) | (swizzle << 17) | (unknown << 25) | (address << 51)
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instruction_stream += [(LDST, b)]
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elif ins_op in t6xx_alu_ops:
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op = t6xx_alu_ops[ins_op]
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(reg_out, mask, out_component, half0, upper0) = decode_masked_reg(p[1][0], True)
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(_, reg_in1, swizzle1, half1, upper1, mod1) = decode_reg(p[1][1])
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(immediate, reg_in2, swizzle2, half2, upper2, mod2) = decode_reg(p[1][2])
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if immediate:
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register_word = (reg_in1 << 0) | ((reg_in2 >> 11) << 5) | (reg_out << 10) | (1 << 15)
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else:
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register_word = (reg_in1 << 0) | (reg_in2 << 5) | (reg_out << 10)
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if ins_mod in ["vadd", "vmul", "lut"]:
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io_mode = t6xx_reg_mode["half" if half0 else "full"]
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repsel = 0
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i1half = half1
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i2block = 0
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output_override = 2 # NORMAL, TODO
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wr_mask = 0
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if (ins_outmod == "quarter"):
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io_mode = t6xx_reg_mode["quarter"]
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if half0:
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# TODO: half actually
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repsel = 2 * upper1
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else:
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repsel = upper1
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if half0:
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# Rare case...
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(_, halfmask, _, _, _) = decode_masked_reg(p[1][0], False)
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wr_mask = halfmask
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else:
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wr_mask = mask
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if immediate:
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# Inline constant: lower 11 bits
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i2block = ((reg_in2 & 0xFF) << 3) | ((reg_in2 >> 8) & 0x7)
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else:
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if half0:
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# TODO: replicate input 2 if half
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pass
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else:
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# TODO: half selection
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i2block = upper2 | (half2 << 2)
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i2block |= swizzle2 << 3
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# Extra modifier for some special cased stuff
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try:
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special = ins.split(".")[3]
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if special == "low":
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output_override = 0 # low
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elif special == "fulllow":
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# TODO: Not really a special case, just a bug?
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io_mode = t6xx_reg_mode["full"]
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output_override = 0 #low
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wr_mask = 0xFF
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except:
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pass
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instruction_word = (op << 0) | (io_mode << 8) | (mod1 << 10) | (repsel << 12) | (i1half << 14) | (swizzle1 << 15) | (mod2 << 23) | (i2block << 25) | (output_override << 36) | (out_mod << 38) | (wr_mask << 40)
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elif ins_mod in ["sadd", "smul"]:
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# TODO: What are these?
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unknown2 = 0
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unknown3 = 0
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i1comp_block = 0
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if half1:
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i1comp_block = swizzle1 | (upper1 << 2)
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else:
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i1comp_block = swizzle1 << 1
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i2block = 0
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if immediate:
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# Inline constant is splattered in a... bizarre way
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i2block = (((reg_in2 >> 9) & 3) << 0) | (((reg_in2 >> 8) & 1) << 2) | (((reg_in2 >> 5) & 7) << 3) | (((reg_in2 >> 0) & 15) << 6)
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else:
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# TODO: half register
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swizzle2 = (swizzle2 << 1) & 0x1F
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i2block = (mod2 << 0) | ((not half2) << 2) | (swizzle2 << 3) | (unknown2 << 5)
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outcomp_block = 0
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if True:
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outcomp_block = out_component << 1
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else:
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# TODO: half register
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pass
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instruction_word = (op << 0) | (mod1 << 8) | ((not half1) << 10) | (i1comp_block << 11) | (i2block << 14) | (unknown3 << 25) | (out_mod << 26) | ((not half0) << 28) | (outcomp_block) << 29
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else:
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instruction_word = op
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instruction_stream += [(ALU, ins_mod, register_word, instruction_word)]
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elif family == "texture":
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# Texture ops use long series of modifiers to describe their needed
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# capabilities, seperated by dots. Decode them here
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parts = ins.split(".")
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# First few modifiers are fixed, like an instruction name
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tex_op = parts[1]
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tex_fmt = parts[2]
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# The remaining are variable, but strictly ordered
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parts = parts[3:]
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op = texture_op[tex_op]
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# Some bits are defined directly in the modifier list
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shadow = "shadow" in parts
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cont = "cont" in parts
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last = "last" in parts
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has_filter = "raw" not in parts
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# The remaining need order preserved since they have their own arguments
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argument_parts = [part for part in parts if part not in ["shadow", "cont", "last", "raw"]]
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bias_lod = 0
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for argument, part in zip(argument_parts, arguments[4:]):
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if argument == "bias":
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bias_lod = int(float(part) * 256)
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else:
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print("Unknown argument: " + str(argument))
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fmt = texture_fmt[tex_fmt]
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has_offset = 0
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magic1 = 1 # IDEK
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magic2 = 2 # Where did this even come from?!
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texture_handle = int(arguments[1][len("texture"):])
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sampler_parts = arguments[2].split(".")
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sampler_handle = int(sampler_parts[0][len("sampler"):])
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swizzle0 = standard_swizzle_from_parts(sampler_parts)
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(full0, select0, upper0, mask0) = decode_texture_out_reg(arguments[0])
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(full1, select1, upper1, swizzleR1, swizzleL1) = decode_texture_reg(arguments[3])
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|
||||
tex = (op << 0) | (shadow << 6) | (cont << 8) | (last << 9) | (fmt << 10) | (has_offset << 15) | (has_filter << 16) | (select1 << 17) | (upper1 << 18) | (swizzleL1 << 19) | (swizzleR1 << 21) | (0 << 23) | (magic2 << 25) | (full0 << 29) | (magic1 << 30) | (select0 << 32) | (upper0 << 33) | (mask0 << 34) | (swizzle0 << 40) | (bias_lod << 72) | (texture_handle << 88) | (sampler_handle << 104)
|
||||
|
||||
instruction_stream += [(TEXTURE, tex)]
|
||||
elif family == "br":
|
||||
cond = ins.split(".")[2]
|
||||
condition = branch_condition[cond]
|
||||
bop = compact_branch_op[ins_op]
|
||||
|
||||
offset = int(arguments[0].split("->")[0])
|
||||
|
||||
# 2's complement and chill
|
||||
if offset < 0:
|
||||
offset = (1 << 7) - abs(offset)
|
||||
|
||||
# Find where we're going
|
||||
dest_tag = int(arguments[0].split("->")[1])
|
||||
|
||||
br = (bop << 0) | (dest_tag << 3) | (offset << 7) | (condition << 14)
|
||||
|
||||
# TODO: Unconditional branch encoding
|
||||
|
||||
instruction_stream += [(ALU, "br", None, br)]
|
||||
elif ins[1:] == "constants":
|
||||
if ins[0] not in constant_types:
|
||||
print("Unknown constant type " + str(constant_type))
|
||||
break
|
||||
|
||||
(fmt, cast) = constant_types[ins[0]]
|
||||
|
||||
encoded = [struct.pack(fmt, cast(f)) for f in p[1]]
|
||||
|
||||
consts = bytearray()
|
||||
for c in encoded:
|
||||
consts += c
|
||||
|
||||
# consts must be exactly 4 quadwords, so pad with zeroes if necessary
|
||||
consts += bytes(4*4 - len(consts))
|
||||
|
||||
instruction_stream += [(ALU, "constants", consts)]
|
||||
|
||||
# Emit from instruction stream
|
||||
instructions = []
|
||||
index = 0
|
||||
while index < len(instruction_stream):
|
||||
output_stream = bytearray()
|
||||
ins = instruction_stream[index]
|
||||
tag = ins[0]
|
||||
|
||||
can_prefetch = index + 1 < len(instruction_stream)
|
||||
succeeding = None
|
||||
|
||||
if tag == LDST:
|
||||
succeeding = instruction_stream[index + 1] if can_prefetch else None
|
||||
parta = ins[1]
|
||||
partb = None
|
||||
|
||||
if succeeding and succeeding[0] == LDST:
|
||||
partb = succeeding[1]
|
||||
index += 1
|
||||
else:
|
||||
partb = parta
|
||||
parta = t6xx_load_store_ops["ld_st_noop"]
|
||||
|
||||
tag8 = t6xx_tag["load_store"]
|
||||
|
||||
ins = (partb << 68) | (parta << 8) | tag8
|
||||
output_stream += (ins.to_bytes(16, "little"))
|
||||
elif tag == TEXTURE:
|
||||
tag8 = t6xx_tag["texture"]
|
||||
ins = (ins[1] << 8) | tag8
|
||||
|
||||
output_stream += (ins.to_bytes(16, "little"))
|
||||
elif tag == ALU:
|
||||
# TODO: Combining ALU ops
|
||||
|
||||
emit_size = 4 # 32-bit tag always emitted
|
||||
|
||||
tag = 0
|
||||
register_words = bytearray()
|
||||
body_words = bytearray()
|
||||
constant_words = None
|
||||
|
||||
last_alu_bit = 0
|
||||
|
||||
# Iterate through while there are ALU tags in strictly ascending order
|
||||
while index < len(instruction_stream) and instruction_stream[index][0] == ALU and t6xx_alu_bits[instruction_stream[index][1]] > last_alu_bit:
|
||||
ins = instruction_stream[index]
|
||||
|
||||
bit = t6xx_alu_bits[ins[1]]
|
||||
last_alu_bit = bit
|
||||
|
||||
if ins[1] == "constants":
|
||||
constant_words = ins[2]
|
||||
else:
|
||||
# Flag for the used part of the GPU
|
||||
tag |= 1 << bit
|
||||
|
||||
# 16-bit register word, if present
|
||||
if ins[2] is not None:
|
||||
register_words += (ins[2].to_bytes(2, "little"))
|
||||
emit_size += 2
|
||||
|
||||
size = int(t6xx_alu_size_bits[ins[1]] / 8)
|
||||
body_words += (ins[3].to_bytes(size, "little"))
|
||||
emit_size += size
|
||||
|
||||
index += 1
|
||||
|
||||
index -= 1 # fix off by one, from later loop increment
|
||||
|
||||
# Pad to nearest multiple of 4 words
|
||||
padding = (16 - (emit_size & 15)) if (emit_size & 15) else 0
|
||||
emit_size += padding
|
||||
|
||||
# emit_size includes constants
|
||||
if constant_words:
|
||||
emit_size += len(constant_words)
|
||||
|
||||
# Calculate tag given size
|
||||
words = emit_size >> 2
|
||||
tag |= t6xx_tag["alu" + str(words)]
|
||||
|
||||
# Actually emit, now that we can
|
||||
output_stream += tag.to_bytes(4, "little")
|
||||
output_stream += register_words
|
||||
output_stream += body_words
|
||||
output_stream += bytes(padding)
|
||||
|
||||
if constant_words:
|
||||
output_stream += constant_words
|
||||
|
||||
instructions += [output_stream]
|
||||
index += 1
|
||||
|
||||
# Assmebly over; just emit tags at this point
|
||||
binary = bytearray()
|
||||
|
||||
for (idx, ins) in enumerate(instructions):
|
||||
# Instruction prefetch
|
||||
tag = 0
|
||||
|
||||
if idx + 1 < len(instructions):
|
||||
tag = instructions[idx + 1][0] & 0xF
|
||||
|
||||
# Check for ALU special case
|
||||
|
||||
if is_tag_alu(tag) and idx + 2 == len(instructions):
|
||||
tag = 1
|
||||
else:
|
||||
# Instruction stream over
|
||||
|
||||
tag = 1
|
||||
|
||||
ins[0] |= tag << 4
|
||||
|
||||
binary += ins
|
||||
|
||||
pprint.pprint(program)
|
||||
|
||||
with open(sys.argv[2], "wb") as f:
|
||||
f.write(binary)
|
||||
Loading…
Reference in New Issue